Method and system for asynchronous chip design

Details Method and system for asynchronous chip design Method and system for asynchronous chip design

2008-10-17

2011-11-22

Lin, Sun (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S100000, C716S108000, C716S134000

Reexamination Certificate

active

08065647

ABSTRACT:
A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control logic for the first pipeline stage is implemented using a template that contains characterization information for timing to generate an asynchronous circuit design.

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