Method and system for area efficient charge-based...

Details Method and system for area efficient charge-based... Method and system for area efficient charge-based...

2006-09-12

2006-09-12

Nguyen, Ha Tran (Department: 2829)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

C324S765010, C324S1540PB

Reexamination Certificate

active

07106073

ABSTRACT:
The present invention is directed to a system for area efficient charge-based capacitance measurement requiring a minimum silicon area for probe pads. A structure block for the system includes several test structures coupled to a target test capacitance structure, a reference structure, and a logic block. Each test structure is coupled to a corresponding test capacitance structure. The logic block coupled to the several test structures selects a desirable test structure from the several test structures. The system may include several structure blocks and an additional logic block to select a desirable structure block. Each structure block includes a single output pin for busing each test output from the several test structures. In this manner, the silicon area may be minimized through reduction of the number of total pins and probe pads required.

REFERENCES:
patent: 5212454 (1993-05-01), Proebsting
patent: 6300765 (2001-10-01), Chen
patent: 6934669 (2005-08-01), Suaya et al.
IEEE Electron Device Letters; vol. 18, No. 1, Jan. 1997; A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement; Bruce W. McGaughy, James C. Chen, Dennis Sylvester and Chenming Hu.

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