Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-06-04
2011-11-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S108000
Reexamination Certificate
active
08056035
ABSTRACT:
A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
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Buck Nathan C.
Dreibelbis Brian M.
Dubuque John P.
Foreman Eric A.
Habitz Peter A.
International Business Machines - Corporation
Kotulak Richard
Roberts Mlotkowski Safran & Cole P.C.
Siek Vuthe
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