Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Patent
1998-04-02
1999-12-07
Chaudhari, Chandra
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
438401, 438975, H01L 2100
Patent
active
059982268
ABSTRACT:
The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.
REFERENCES:
patent: 3808527 (1974-04-01), Thomas
patent: 4386459 (1983-06-01), Boulin
patent: 5332470 (1994-07-01), Crotti
patent: 5770995 (1998-06-01), Kamiya
patent: 5904563 (1999-05-01), Yu
Chaudhari Chandra
LSI Logic Corporation
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