Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2006-05-30
2006-05-30
Thai, Luan (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S975000, C438S462000, C257S797000, C257SE23179
Reexamination Certificate
active
07052968
ABSTRACT:
In a method and system for placing an IC (integrated circuit) die onto a package substrate, a first reference is determined after locating a first fiducial on the package substrate, and a second reference is determined after locating a second fiducial on the package substrate. The IC die is placed onto the package substrate to be aligned with respect to the first and second references of the first and second fiducials that are comprised of a plurality of markings such as a plurality of dots.
REFERENCES:
patent: 5528372 (1996-06-01), Kawashima
patent: 5952247 (1999-09-01), Livengood et al.
patent: 6548764 (2003-04-01), Prindiville et al.
patent: 6593168 (2003-07-01), Ehrichs et al.
patent: 6668449 (2003-12-01), Rumsey et al.
patent: 6811938 (2004-11-01), Tutt et al.
patent: 6938335 (2005-09-01), Kuribayashi et al.
patent: 2003/0027342 (2003-02-01), Sheridan et al.
Dubey Ajit
Lee Swee Peng
Advanced Micro Devices , Inc.
Choi Monica H.
Thai Luan
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