Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-09-10
2001-05-01
Cuchlinski, Jr., William A. (Department: 3661)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S003000, C700S069000, C700S250000, C700S258000, C700S275000, C701S025000, C701S220000, C324S426000, C324S430000, C327S103000, C327S362000, C327S561000, C341S118000, C341S119000, C341S112000, C341S167000, C708S823000
Reexamination Certificate
active
06226562
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to integrated circuits. In particular, the present invention relates to integrated circuit design. More particularly, the present invention relates to techniques for adjusting and calibrating circuit parameters within an integrated circuit. Still more particularly, the present invention relates to analog integrated circuits and techniques for calibrating and adjusting such circuits.
2. Description of the Related Art
It is desirable to be able to adjust the performance of semiconductor integrated circuits after processing has been completed to minimize variation associated with process tolerance. This adjustment or calibration procedure should be able to be applied to multiple interacting or non-interacting circuits on the same semiconductor die. It is desirable to be able to iterate the adjustment or change particular circuits to counteract changes in circuit performance caused by circuit interaction. For example, if circuit A is calibrated before circuit B and the subsequent calibration of circuit B changes the performance of circuit A, it is desirable to iterate circuit A's calibration. It is also desirable to accomplish this calibration or adjustment without increasing process complexity substantially.
Memory circuits, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have been a prime technology driver for semiconductor processing. As a result, most modern complementary metal oxide semiconductor (CMOS) and BICMOS processes are derivatives of semiconductor processes developed for memories. Most memory circuits have the capability of utilizing the redundancy fuses needed to replace a bad bank of memory on a chip. These fuses can take the form of metal or polysilicon straps or links that are blown with a laser or electrically blown. Because of the price sensitivity of memory, fuse blow processes have been optimized for low cost and equipment to blow the fuses is readily available. However, a problem with utilizing fuses to calibrate integrated circuits is that fuses are not iterative in nature.
Techniques have thus been developed to calibrate circuits, particularly analog integrated circuits, by adjusting fuses at the wafer level. However, such techniques are not useful when calibrating and adjusting circuit parameters for a variety of different analog circuits on a single integrated circuit chip. Analog circuits possess varying degrees of sensitivity to technology variations and packaging mechanical stresses which results in non-optimum circuit performance. The performance of analog circuits can be improved by adding calibration circuitry to each analog circuit that adjusts and cancels out technology variations. However, the number of analog circuits can be quite large and often results in several circuits needing calibration. Based on the foregoing, it can be appreciated that what is needed to successfully calibrate a variety of diverse analog circuits on a single chip is a method and system that avoids the use of fuse adjustment calibration techniques and an overabundance of calibration circuitry. To minimize chip size and cost, what is needed is a generic calibrate circuit or engine that can be utilized to calibrate all analog circuits on a single integrated circuit chip.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved method and system for calibrating integrated circuits.
It is another object of the present invention to provide an improved method and system for calibrating analog integrated circuits.
It is yet another object of the present invention to provide an improved method and system for calibrating and adjusting analog integrated circuits.
It is still another object of the present invention to provide a generic calibration circuit that may be integrated and utilized to calibrate and adjust a variety of diverse analog integrated circuits on a single integrated circuit chip.
The above and other objects are achieved as is now described. A method and system for calibrating analog integrated circuits are disclosed. Initially, a single calibration circuit is formed integral with a group of analog integrated circuits. A control signal and a calibration signal are generated from the calibration circuit. Next, the control signal and the calibration signal are selectively coupled to an input of a particular analog integrated circuit among the group of analog integrated circuits. The particular analog integrated circuit is then enabled for calibration via the control signal. An output of the particular analog integrated circuit is thereafter observed, in response to enabling the particular analog integrated circuit for calibration via the control signal, such that if an output of the particular analog integrated circuit corresponds to the calibration signal, a successful calibration of the particular analog integrated circuit is indicated, thereby permitting the single calibration circuit to generically calibrate a multitude of diverse analog integrated circuits. Thereafter, at least one other analog integrated circuit among the group of integrated circuits may be calibrated. The output of the particular analog integrated circuit is coupled to an input of the single calibration circuit, and the calibration value is incremented until the particular analog integrated circuit is calibrated, such that upon completion of the calibration, the calibration value comprises a current calibration value associated with the particular analog integrated circuit. In addition, if the output of the particular analog integrated circuit is composed of a logically high value, then an indication is provided that the particular analog integrated circuit has been successfully calibrated.
REFERENCES:
patent: 4092726 (1978-05-01), Schoeff
patent: 4881038 (1989-11-01), Champlin
patent: 5396130 (1995-03-01), Galbraith et al.
Zupancic, A calibration technique in robotic assembly of hybrid circuits, IEEE., pp. 137-146, 1990.*
Michael et al., An automated flip-chip assembly technology for advanced VLSI packaging, IEEE., pp. 335-341, 1988.*
Shieh et al., DC Control and Observation Structures for Analog Circuits., IEEE., pp. 120-123, 1995.
Cuchlinski Jr. William A.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Marc McDieunel
LandOfFree
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