Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-02-24
2001-08-28
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S221000, C712S234000
Reexamination Certificate
active
06282628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and system for data processing or information handling systems in general and, in particular, to a method and system for processing vector data in a computer system. Still more particularly, the present invention relates to a method and system for producing a two-bit code result when performing a single instruction multiple data (SIMD) predicate compare operation in three-dimensional graphic operations.
2. Description of the Prior Art
Applications of modern computer systems are requiring greater speed and data handling capabilities for uses such as multimedia and scientific modeling. For example, multimedia systems generally are designed to perform video and audio data compression, decompression, and high-performance manipulation such as three-dimensional imaging and graphics. Three-dimensional imaging and graphics require massive data manipulation and an extraordinary amount of high-performance arithmetic and vector-matrix operations. One such operation is the classical single-instruction multiple-data (SIMD) predicate comparison operation which involves comparing the contents of two vector registers, element by element, for a specific predicate (e.g. is greater than, is less than or is equal to) in producing three-dimensional graphics. For each element the result of the comparison (true or false) is placed in the respective element of a target vector register. The control flow for this type of operation is typically handled in parallelism by executing the operations on all paths of a branch and saving the results in separate registers. A mask or set of masks is then generated based on the condition of the branch wherein the mask(s) are used to perform an element-by-element select between the possible results. This procedure works well for loop-based data parallelism and is efficiently supported using single-instruction multiple-data (SIMD) predicate comparison operations.
However, there are cases when data-driven control flow in instruction sequencing controlled by the results of operations on data is needed to accommodate the occurrence of special events, where specialized data handling is needed in the presence of these events. These special events could manifest themselves in a single element, across all elements, or in no elements at all in a single-instruction multiple-data (SIMD) predicate comparison operation. Additionally, these special events may severely reduce or even eliminate the use of SIMD parallelism. Therefore, there is a need for a method and system that allows control flow using conditional branching on the special event when all comparisons are false or when all predicate comparison results are true. The subject invention herein solves this problem in a new and unique manner that has not been part of the art previously.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to provide an improved method and system for performing single-instruction multiple-data (SIMD) predicate compare operations in a computer system or information handling system.
It is another object of the present invention to provide an improved method and system when performing a single-instruction multiple-data (SIMD) predicate compare operation that produces a two-bit code result for use in three-dimensional graphic operations when generating three-dimensional images and graphics in a computer system or information handling system.
The foregoing objects are achieved as is now described. The present invention summarizes the results of a classical single-instruction multiple-data SIMD predicate comparison operation, signaling whether all predicate comparisons resulted in a false result or true result, and placing that status into a separate status register, such as the Power PC Condition Register. The method and system utilizes first and second status bits to support the signaling whether all element predicate comparisons resulted in true or false. The first status bit is set when all element predicate comparisons resulted in false (i.e. a NOR of all predicate comparison results), and the second status bit is set when all element predicate comparisons resulted in true (i.e. an AND of all predicate comparison results). This capability allows control flow using conditional branching on the event when all predicate comparison results are false or when all predicate comparison results are true. The method and system of the present invention is useful in 3-D graphics such as lighting and trivial acceptance testing where executing down both paths of a branch and then selecting the correct result is not tolerable.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Diefendorff Keith Everett
Dubey Pradeep Kumar
Hochsprung Ronald Ray
Olsson Brett
Scales, III Hunter Ledbetter
An Meng-Al T.
Bracewell & Patterson L.L.P.
Chang Jung-won
International Business Machines - Corporation
Salys Casimer K.
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