Cryptography – Particular algorithmic function encoding
Reexamination Certificate
2007-03-20
2007-03-20
Revak, Christopher (Department: 2136)
Cryptography
Particular algorithmic function encoding
C708S491000, C708S492000
Reexamination Certificate
active
09970901
ABSTRACT:
A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.
REFERENCES:
patent: 4949301 (1990-08-01), Joshi et al.
patent: 5187783 (1993-02-01), Mansfield et al.
patent: 5289397 (1994-02-01), Clark et al.
patent: 5349551 (1994-09-01), Petro
patent: 5479365 (1995-12-01), Ogura
patent: 5572454 (1996-11-01), Lee et al.
patent: 5724279 (1998-03-01), Benaloh et al.
patent: 5828590 (1998-10-01), Chen et al.
patent: 6085210 (2000-07-01), Buer
patent: 6141422 (2000-10-01), Rimpo et al.
patent: 6151393 (2000-11-01), Jeong
patent: 6182104 (2001-01-01), Foster et al.
patent: 6209016 (2001-03-01), Hobson et al.
patent: 6748410 (2004-06-01), Gressel et al.
patent: 6772300 (2004-08-01), Manseau
patent: 2001/0010077 (2001-07-01), McGregor et al.
patent: 2002/0010730 (2002-01-01), Blaker
patent: 2002/0039418 (2002-04-01), Dror et al.
patent: 2002/0186837 (2002-12-01), Hopkins et al.
patent: 2005/0185791 (2005-08-01), Chen et al.
Grossschaedl J: “A Bit-Serial Unified Multiplier Architecture for Finite Fields GF (P) and GF (2M)” Cryptographic Hardware and Embedded Systems. 3rdInternational Workshop, Ches 2001, Paris France, May 14-16, 2001 Proceedings; Lecture Notes in Computer Science, Berlin: Springer, De, vol. 2162, May 14, 2001, pp. 202-219.
Koc, Cetin Kaya,High-Speed RSA Implementation, RSA Laboratories, Version 2.0, Nov. 1994, 70 Pages.
U.S. Non-Provisional Application titled Circuit and Method for Performing Multiple Modulo Mathematic Operations by Takahashi et al., filed concurrently herewith.
Lahti Gregg D.
Langston R. Vaughn
Takahashi Richard J.
Corrent Corporation
Ingrassia Fisher & Lorenz
Revak Christopher
Shiferaw Eleni
LandOfFree
Method and system for a full-adder post processor for modulo... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for a full-adder post processor for modulo..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for a full-adder post processor for modulo... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3781336