Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-07-18
2010-06-08
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185240, C365S185260, C365S185270, C365S185280, C365S185290, C365S185330
Reexamination Certificate
active
07733700
ABSTRACT:
A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vccto, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than Vcc. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage). The substrate voltage to the drain voltage can not exceed the avalanche multiplication junction breakdown for a small programming current during the bias voltage adjustment.
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Flashsilicon, Inc.
Haynes and Boone LLP
Phan Trong
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