Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
1999-08-06
2001-09-18
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
Reexamination Certificate
active
06291307
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating an analog capacitor on the surface of a Field Oxide isolation region.
(2) Description of the Prior Art
The manufacturing of semiconductor devices is an amalgam of the creation of a variety of components that collectively perform functions of data manipulation (logic functions) and of data retention (storage functions). The vast majority of these functions operates in a digital or one-off mode and as such recognizes zero and one conditions within the operational levels of the circuits. There are, in addition, applications that make use of analog levels of voltage where the voltage may have a spectrum of values between a high limit and a low limit. There are furthermore applications where both the digital and the analog methods of signal processing reside side by side in the same semiconductor device.
This mixture of functions and processing capabilities brings with it a mixture of components that can coexist within one semiconductor device. Where the vast majority of device components is made up of transistors, gate electrodes and a variety of switching components that address logic processing functions, it is not uncommon to also see resistors and capacitors that form part of a semiconductor device. It is for instance known that capacitors form a basic component of many analog circuits that are used for analog applications such as switched capacitor filters. It is also well known in the art that capacitors are widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor.
A resistive load is one of the components that is required for, for instance, Static Random Access Memory (SRAM) devices. A resistive load component can, in its simplest form, be created by sandwiching a lightly doped layer of polysilicon between two points of electrical contact. To the points of electrical contact can be connected for instance metal or polysilicon interconnect lines or interconnect lines that are created by N+ diffusion thereby forming low resistance interconnect lines. The sandwiched layer of poly serves as a resistor, which typically has a high resistive value. The resistive value depends on the level of doping that is applied to the layer of poly and by the geometric configuration (cross section) of the resistor. Where the resistor load is applied to the SRAM, the resistor must make electrical contact with the gate electrode and the drain region of the pull-down transistor as well as to the metal line to pass gate transistor. A resistor tab that makes contact with the gate and the drain regions can be created by depositing dopants at the interfaces between these regions and the resistive load. The resistive load is typically interconnected to its surrounding components by means of a high dope implant on either side of the resistor for which a doping mask is used.
As already indicated, capacitors form an important part of a number of semiconductor circuit designs. Where a capacitor is used as a functional component of an analog integrated circuit (IC), the capacitor is used to assure functionality of the analog circuit. Where a capacitor is used as a functional component of a digital integrated circuit, the capacitor is used to provide charge storage locations for individual bits of digital data that are stored within the digital IC.
One of the first processing steps that is required in creating semiconductor components on the surface of a substrate is to electrically isolate the active regions (the regions where the devices will be created) on the substrate surface. For this purpose, Field Oxide (FOX) isolation regions can be used to isolate discrete devices, such as for instance Field Effect Transistors (FET's), in Ultra Large Scale Integrated (ULSI) circuits on semiconductor chips. Another conventional approach in the semiconductor industry for forming field isolation is by the Local Oxidation of Silicon (LOCOS) method. LOCOS uses a patterned silicon nitride (Si
3
N
4
) as an oxidation barrier mask, the underlying silicon substrate is selectively oxidized to form the semi-planar isolation. However, this method requires long oxidation times (a large thermal budget) while lateral oxidation under the barrier mask limits the minimum spacing between adjacent active device areas. This prevents further increasing of the device packaging density.
One method of circumventing the LOCOS limitations and to further reduce the field oxide (FOX) minimum feature size is to allow shallow trench isolation (STI). One method of making STI is to first etch trenches having essentially vertical sidewalls in the silicon substrate. The trenches are then filled with a CVD of silicon oxide (SiO
2
) and the SiO
2
is then plasma etched back or polished back using CMP, to form the STI isolation region. However, there are several problems associated with the conventional or prior art shallow trench isolation techniques. For example, if the silicon oxide is etched or polished to the substrate surface, dishing can occur resulting in a concave surface of the CVD silicon oxide in the trenches. Unfortunately, this results in recesses in the field oxide at the edge of the device areas. Later, when the gate electrodes are made for the FET's extending over the device area edge, this results in an undesirable lower and variable threshold voltage when the devices are completed. Therefore it is desirable to make FOX areas that extend higher than the substrate surface to avoid this problem while reducing manufacturing costs.
FIG. 1
shows a Prior Art processing sequence that is used to create an integrated circuit that contains a number of Field Effect Transistors (FET's) and a capacitor.
FIG. 1
a
shows a monocrystalline silicon semiconductor substrate
10
into which two FOX regions
12
and
14
have been created. A layer
16
of for instance poly 1 is blanket deposited over the surfaces and patterned by lithography and etching techniques to leave the poly 1 layer
16
as the bottom plate for the capacitor on the surface of the recessed isolation region
14
. An interpoly layer
18
composed of for instance silicon oxide or tetraethylorthosilicate (TEOS) are deposited and patterned by lithography and etching techniques to give the structure as shown in
FIG. 1
a.
Layer
16
forms the bottom plate for the capacitor; layer
18
forms the capacitor dielectric.
FIG. 1
b
shows the blanket deposition of a layer
20
of for instance poly 2 over the surface of the components. Lithography and etching of layer
20
is accomplished by the formation of resist masking of layer
22
as shown in
FIG. 1
c.
The etching leaves the top plate
24
for the capacitor and the gate electrode
22
of the field effect transistor in place. The layers
26
of photoresist are removed by the conventional process of ashing.
FIG. 1
d
shows the completion of the structure by first implanting the self-aligned Lightly Doped diffusion (LDD) regions
28
adjacent to the gate electrode structure
22
, by forming the gate spacers
30
, by creating the (heavily doped) source and drain regions
32
and
34
respectively for the gate electrode
22
, the blanket deposition and subsequent patterning and etching of the passivation layer
36
and the establishment of metal contacts
38
(to the source region of the gate electrode
22
),
40
(to the drain region of the gate electrode
22
) and
42
(to the top plate of the capacitor).
It has already been pointed out that, when the Shallow Trench Isolation (STI) method of active device isolation is used, a field oxide regions is typically not flat due to the dishing effects that occur during the planarization, using Chemical Mechanical Polishing (CMP) techniques, of the field oxide layer. This results in difficulties in creating th
Chu Shao-Fu Sanford
Pan Yang
Shao Kai
Yimin Wang
Chartered Semiconductor Manufacturing Ltd.
Coleman William David
Pham Long
Pike Rosemary L.S.
Saile George O.
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