Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-02-26
2001-12-04
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C029S831000
Reexamination Certificate
active
06326555
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to multi-layer circuit substrates, as well as structures, methods and materials for making the same. The multilayer circuit substrates can be used as, for example, a MCM (multichip module) substrate or a high density mother board.
BACKGROUND OF THE INVENTION
Multilayer circuit substrates are used to interconnect a large number of integrated circuit chips. Such substrates typically have a large number of signal lines between the chips as well as several layers of signal lines separated by interleaving dielectric layers. Via structures can electrically couple signal lines in different planes of the substrate. Because via structures can conduct electricity in a direction generally vertical to the planar direction of the substrate, they are sometimes called “z-connections”. The signal lines and dielectric layers are typically made in a “build-up” process. In typical build-up process, conducting and dielectric layers may be formed sequentially by a variety of operations including metal deposition, photolithography, and etching. Build-up processes such as these involve many steps and are quite costly. Furthermore, a defect in the formation of one layer during the build-up process could potentially ruin the entire substrate. Current trends in the industry are toward increasing the density and decreasing the size of signal lines and via structures in the substrate. This, in turn, increases cost of the build-up process and increases the probability of defects.
Furthermore, current trends in the industry are also toward producing via structures having diameters less than about 200 &mgr;m. Reliable via structures in multilayer circuit substrates can sometimes be difficult to form for apertures less than about 200 &mgr;m in diameter, especially in a cost-effective manner. For example, via structures can be formed by depositing a slurry including a polymeric binder and conductive particles into an aperture in a dielectric layer. Conductive particles contact each other in the formed via structure and are bound by the binder which fills the interstices between the particles. The formed via structure can contact conductive pads disposed at opposite ends of the via structure, thus providing electrical communication between different planes in a substrate. One problem with this type of via structure is that the amount of conductive material which can be deposited in the aperture is dependent upon how efficiently the conductive particles are packed within the aperture. Conductivity relies on the contact between the particles, and the particles and mating pads or metallization on the aperture walls. The interstices between the conductive particles are filled with the binder which is non-conductive, thus limiting the conductivity of the via structure as a whole.
Accordingly, there is a need for reliable, efficient, and less expensive methods, materials, and structures for forming multilayer circuit substrates.
SUMMARY OF THE INVENTION
A first inventive concept relates to structures having conductive bumps and methods of forming and using these structures to make multilayer printed circuit substrates. The methods include: forming a laminate comprising a first circuitized layer having a first conductive region, a bonding sheet (preferably thermoplastic), and a release layer, wherein the bonding sheet is disposed between the first circuitized layer and the release layer; forming an aperture in the bonding sheet and the release layer to expose the first conductive region; depositing a conductive composition within the aperture; reflowing the conductive composition while the conductive composition is within the aperture to form a conductive bump; separating the release layer from the bonding sheet; and laminating a second circuitized layer having a second conductive region to the first circuitized layer so that the conductive region of the second circuitized layer is electrically coupled to the conductive bump.
A second inventive concept relates to a microencapsulating composition, microencapsulated particles, and methods for making multilayer printed circuit substrates using microencapsulating compositions and microencapsulated particles. The microencapsulating composition can be used in conjunction with any suitable stenciling process, and includes conductive particles and a carrier. The carrier includes a low viscosity resin, a fluxing agent, and a solvent. The microencapsulating composition can form a plurality of microencapsulated conductive particles, which are used to form a via structure in a multilayer printed circuit substrate.
Multilayer circuit substrates formed according to the first or second inventive concepts can be incorporated into any suitable electrical assembly. Exemplary assemblies include a chip modules such as multichip modules or single chip modules, as well as grid array packages such as ball grid arrays or pin grid arrays. In such electrical assemblies one or more chips can be disposed on the multilayer circuit substrate and can be in electrical communication with a via structure in the multilayer circuit substrate. The electrical assemblies can also include one or more multilayer ceramic circuit substrates or rigid polymeric wiring boards in any suitable combination or permutation with a flexible, rigid polymeric, or ceramic multilayer circuit substrate.
These and other aspects of the first and second inventive concepts will become apparent to those skilled in the art from the following detailed description, the accompanying drawings, and the appended claims. Aspects of the first and second inventive concepts can be used separately or together in any suitable manner.
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Beilin Solomon I.
Jiang Hunt Hang
Massingill Thomas J.
McCormack Mark Thomas
Coudert Brothers
Cuneo Kamand
Fujitsu Limited
Gaffin Jeffrey
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