Method and structure of ternary CAM cell in logic process

Details Method and structure of ternary CAM cell in logic process Method and structure of ternary CAM cell in logic process

2000-07-19

2002-04-09

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S154000, C365S190000

Reexamination Certificate

active

06370052

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) cells. More specifically, the present invention relates to a space-efficient ternary CAM cell fabricated using standard ASIC or logic processes.
BACKGROUND OF THE INVENTION
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address in an array. In a CAM cell array, a specified data string, or comparand, is compared to the data stored in each row of CAM cells. A match signal is generated by any row of CAM cells containing data that matches the comparand.
FIG. 1
shows a conventional CAM cell
100
as described in U.S. Pat. No. 4,833,643, issued May 23, 1989 to Hori. CAM cell
100
comprises a static random access memory (SRAM) cell
110
, a match circuit
120
, a word line WL, a bit line BL, a complementary bit line /BL, and a match line ML. SRAM cell
110
comprises NMOS access transistors
101
and
102
, a data storage structure
103
, and data storage nodes N
1
and N
2
. Access transistor
101
is coupled between bit line BL and node N
1
, while access transistor
102
is coupled between node N
2
and complementary bit line /BL. The gates of access transistors
101
and
102
are coupled to word line WL.
Match circuit
120
comprises NMOS transistors
121
-
124
. Transistors
121
and
122
are serially coupled between match line ML and ground, thereby forming a stacked transistor string
125
. Transistors
123
and
124
are likewise serially coupled between match line ML and ground, thereby forming a stacked transistor string
126
. The gates of transistors
122
and
124
are connected to bit line BL and complementary bit line /BL, respectively. The gates of transistors
121
and
123
are coupled to data storage nodes N
2
and N
1
, respectively.
During a read or write operation to CAM cell
100
, word line WL is raised to a logic HIGH voltage, thereby turning on access transistors
101
and
102
. Data on bit line BL and complementary bit line /BL is then written to data storage nodes N
1
and N
2
, respectively, or data stored at nodes N
1
and N
2
can be read out to bit lines BL and /BL, respectively.
During a match operation, each bit of the input comparand is compared with a corresponding stored data bit in each row of CAM cells. At the start of the match operation, a data bit B, and a complementary data bit /B, are already stored at nodes N
1
and N
2
, respectively, of SRAM cell
110
. Word line WL is set to a logic LOW voltage and match line ML is precharged to a logic HIGH voltage. A comparand data bit C and its complementary data bit /C are applied to bit lines BL and /BL, respectively. If stored data bits B and /B do not match comparand data bits C and /C, respectively, both transistors in either transistor string
125
or
126
will be on and match line ML will be discharged to ground. If the stored data bits match the comparand data bits, CAM cell
100
does not provide a discharge path for match line ML. This match function performed on bits B and C by match circuit
120
is summarized in Table 1.
TABLE 1
Match Function of CAM Cell 100
Data
Data
Signal Effect On
Bit B
Bit C
Match Line ML
LOW
LOW
Maintain (MATCH)
LOW
HI
Discharge (NO MATCH)
HI
LOW
Discharge (NO MATCH)
HI
HI
Maintain (MATCH)
If any CAM cell in a particular row detects a no-match condition, the match line associated with that row is discharged. Therefore, a match for an input comparand is only indicated if every CAM cell in the row detects a match.
CAM cell
100
is a two-state, or “binary,” device; i.e., the cell can store either a logic LOW or a logic HIGH. However, many modern CAM applications, such as Internet protocol (IP) and asynchronous transfer mode (ATM) communications networks, require a “ternary” storage capability. More specifically, the CAM cells in such applications must be able to store a “DON'T CARE” state that returns a match signal regardless of the compare input.
FIG. 2
shows a ternary CAM cell
200
, as described in U.S. Pat. No. 5,319,590, issued Jun. 7, 1994 to Montoye.
CAM cell
200
provides ternary operation by combining two SRAM memory cells into a single circuit. CAM cell
200
comprises SRAM cells
210
a
and
210
b
bit lines BLa and BLb, complementary bit lines /BLa and /BLb, a word line WL, a match circuit
220
, and a match line ML.
SRAM cells
210
a
and
210
b
are substantially similar to SRAM cell
110
of CAM cell
100
and operate in a similar fashion to store a data bit Ba and data bit Bb (provided via bit lines BLa and BLb, respectively) at data storage nodes N
1
a and N
1
b, respectively.
Match circuit
220
comprises NMOS transistors
221
-
224
. Transistors
221
and
222
are serially coupled between match line ML and ground, forming a stacked transistor string
225
. Transistors
223
and
224
are likewise serially coupled between match line ML and ground, forming a stacked transistor string
226
. The gates of transistors
222
and
224
are connected to bit lines BLa and BLb, respectively. The gates of transistors
221
and
223
are coupled to nodes N
1
a and N
1
b, respectively.
During a write operation to CAM cell
200
, word line WL is raised to a logic HIGH voltage, turning on access transistors
201
a,
202
a,
201
b,
and
202
b.
Data on bit lines BLa and BLb can then be written to data storage nodes N
1
a and N
1
b respectively. Complementary data can be written at the same time to data hold circuits
203
a
and
203
b
from complementary bit lines /BLa and /BLb, respectively. However, for the purposes of CAM cell
200
, only the data stored at nodes N
1
a and N
1
b are relevant. SRAM cells
210
a
and
210
b
therefore operate as “half-cells”, wherein only half of the data stored within those cells is used for comparison purposes. Specifically, the complementary data within cells
210
a
and
210
b
are ignored.
During a typical write operation, a data bit B on bit line BLa and its complementary data bit /B on bit line BLb are stored at nodes N
1
a and N
1
b respectively.For example, to store a logic HIGH in CAM cell
200
, a logic HIGH (bit B) is written to node N
1
a and a logic LOW (bit /B) is written to node N
1
b. Similarly, to store a logic LOW in CAM cell
200
, a logic LOW (bit B) is written to node N
1
a and a logic HIGH (bit /B) is written to node N
1
b.
During a match operation, word line WL is set to a logic LOW voltage, turning off transistors
201
a
and
201
b.
Match line ML is precharged to a logic HIGH voltage, and a comparand data bit C and its complementary data bit /C are applied to bit lines BLb and BLa, respectively. If data bits B and /B are stored in CAM cell
200
, XNOR match circuit
220
performs the comparison in much the same fashion as XNOR match circuit
120
shown in FIG.
1
. If stored data bit B matches comparand data bit C, at least one transistor in each of transistor strings
225
and
226
will be turned off, and match line ML will be maintained at a logic HIGH voltage. If stored data bit B does not match comparand data bit C, both transistors in either transistor string
225
or
226
will be turned on, and match line ML will be discharged to ground.
In addition to the logic HIGH and LOW states described previously, CAM cell
200
can store a logic LOW value at both nodes N
1
a and N
1
b. This “DON'T CARE” state causes CAM cell
200
to indicate a match condition for any comparand data bit C. Specifically, if a “DON'T CARE” state is stored in CAM cell
200
, match circuit
220
is turned off (i.e., transistors
221
and
223
are turned off, disabling stacked transistor strings
225
and
226
, respectively), and match line ML will not be discharged regardless of the value of comparand bit C. These operations of CAM cell
200
are summarized in Table 2.
TABLE 2
Ternary Function of CAM Cell 200
Data
Data
Signal Effect On
Bit B
Bit C
Match Line ML
LOW
LOW
Maintain (MATCH)
LOW
HIGH
Discharge (NO MATCH)
HIGH
LOW
Discharge (NO MATCH)
HIGH
HIGH
Maintain (MATCH)
DON'T
LOW
Maintain (MATCH)
CARE
DON'T
HI
Maintain (MATCH)
CARE

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