Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2006-03-21
2006-03-21
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S397000, C438S653000, C438S672000, C438S687000, C438S738000
Reexamination Certificate
active
07015110
ABSTRACT:
An improved semiconductor integrated circuit device structure. The device structure includes a substrate. A thickness of first insulating material is overlying the substrate. A capacitor region within the thickness of the first insulating material and extends from a lower surface of the first insulating material to an upper surface of the first insulating material. The capacitor region includes a width, which extends from the lower surface to the upper surface. The width may vary slightly in some embodiments. The structure includes a contact region overlying the substrate within at least the capacitor region. A lower capacitor plate formed from a plurality of vertical metal structures defined within the capacitor region and connected to the contact region. Each of the plurality of vertical metal structures includes a width and a height. Each of the plurality of vertical metal structures is substantially parallel to each other along a length of the height of each of the vertical metal structures. A barrier metal layer is formed overlying exposed surfaces of each of the plurality of vertical metal structures. A capacitor dielectric layer is overlying each of the exposed surfaces of the barrier layer on each of the vertical metal structures. An upper capacitor plate is formed from metal material within the capacitor region overlying surfaces of the capacitor dielectric layer. The device structure also has a planarized surface formed from the upper capacitor plate in preferred embodiments.
REFERENCES:
patent: 6451667 (2002-09-01), Ning
patent: 6559004 (2003-05-01), Yang et al.
patent: 6593185 (2003-07-01), Tsai et al.
patent: 6620701 (2003-09-01), Ning
patent: 6638830 (2003-10-01), Tsai et al.
patent: 6706588 (2004-03-01), Ning
patent: 6765255 (2004-07-01), Jin et al.
patent: 2003/0073282 (2003-04-01), Ning
patent: 102 47 454 (2001-10-01), None
Wolf, Ph.D., Stangley, Richard N. Tauber, Ph.D., “Dry Etching for VLSI Fabrication,” Silicon Processing for the VLSI Era—vol. 1: Process Technology, Lattice Press, 1986, pp. 546-550.
Liu et al., Single-Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-01.18um Mixed Mode Signal and System-On-aChip (SoC) Applications, Proc. 2000, 2000, IITC, pp. 111-113.
Semiconductor Manufacturing International (Shanghai) Corporation
Thomas Toniae M.
Townsend and Townsend / and Crew LLP
Wilczewski Mary
LandOfFree
Method and structure of manufacturing high capacitance metal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure of manufacturing high capacitance metal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure of manufacturing high capacitance metal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3585337