Method and structure for suppressing stress-induced defects in i

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

174258, 174250, 428901, H05K 100

Patent

active

053328680

ABSTRACT:
A method for reducing defects in an integrated circuit conductive lines characterized by the steps of providing a conductive line and contacting the conductive line with a layer which reduces stress in the line. There are several mechanisms by which the layer can accomplish the desired stress reduction. One method provides a resilient passivation layer over the conductive line and another method provides a resilient layer beneath the line. Yet another method creates a thin, flexible oxide layer over the conductive line. An extension of this latter method provides a resilient buffer layer over the thin oxide layer and a thick oxide layer over the resilient layer. Another form of stress-reducing layer includes an anti-diffusion layer which reduces the diffusion of metal atoms of the conductive layer into the surrounding oxide. A conductive line structure of the present invention includes at least one conductive line and at least one layer contacting the conductive line which reduces stress in the line. The layer can comprise a resilient layer formed over or beneath the conductive line, or it can include a thin oxide layer disposed over the line. Optionally, the thin oxide layer can be covered with a resilient layer and a thick oxide layer. The layer can also comprise an anti-diffusion layer to reduce diffusion-induced stresses in the conductive line.

REFERENCES:
patent: 4960613 (1990-10-01), Cole et al.
patent: 4988423 (1991-01-01), Yamamato et al.
patent: 5066612 (1991-11-01), Ohba et al.
Sauter et al., "Finite Element Calculations of Thermal Stresses Passivated and Unpassivated Lines Bonded to Substrates" Mat. Res. Soc. Symp. Proc., V.188, Material Research Society, 1990.
Tanikawa, A., "A1 Diffusion into Glass Films Used for the Passivation of Fine A1 Metallization," Journal of the Electrochemical Society, V. 138, No. 10, 1991, pp. 3047-3049.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and structure for suppressing stress-induced defects in i does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and structure for suppressing stress-induced defects in i, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for suppressing stress-induced defects in i will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1054301

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.