Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-02-08
2011-11-08
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
08055878
ABSTRACT:
A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional mesh of parallel processors. The pattern of the designating includes a cyclical repetitive pattern of the parallel processor mesh, as modified to have a skew in at least one dimension so that both a row of data in the array and a column of data in the array map to respective contiguous groupings of the processors such that a dimension of the contiguous groupings is greater than one.
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M. Seetha Lakshimi & Philip S. Yu, Effect of Skew on Join Performance in Parallel Architectures, 107-120 (1988).
Sivan Toledo, et al., “The Design and Implementation of Solar, a Portable Library for Scalable Out-of-Core Linear Algebra Computations”, IBM T.J. Watson Research Center.
Chatterjee Siddhartha
Gunnels John A.
Chan Eddie P
International Business Machines - Corporation
Lindlof John
McGinn IP Law Group PLLC
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