Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-08-21
2001-07-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185040, C365S185090
Reexamination Certificate
active
06266273
ABSTRACT:
INTRODUCTION
1. Technical Field
This invention pertains to the field of semiconductor non-volatile memory architectures and their methods of operating, and has application to flash electrically erasable and programmable read-only memories (EEPROMs).
2. Background
A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. Such subsystems are commonly implemented as either removable memory cards that can be inserted into multiple host systems or as non-removable embedded storage within the host system. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash EEPROM devices are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. A typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks. Each block is further partitioned into one or more addressable sectors that are the basic unit for read and program functions.
The subsystem controller performs a number of functions including the translation of the subsystem's logical block address (LBA) to a physical chip, block, and sector address. The controller also manages the low level flash circuit operation through a series of commands that it issues to the flash memory devices via an interface bus. Another function the controller performs is to maintain the integrity of data stored to the subsystem through various means (e.g. by using an error correction code, or ECC).
In the operation of such systems where the erase block contains multiple sectors, it can occasionally become necessary to copy the contents of one sector's data to another erased sector. This can occur, for example, when the data in a portion of a block's sectors are superseded by new data being written by the host to the subsystem, but the physical proximity of the original sector's new data to the other unaffected sectors' data within the block is to be maintained.
FIG. 1
shows an example of how this can be done. The unaffected sectors' data are read from the original block and are subsequently programmed into erased sectors in another block. The new data from the host are likewise programmed into erased sectors in the new block. After the completion of these operations, the original block with superceded data is erased.
During such an operation as described above, it is necessary when using conventional flash memories to transfer the data from the memory being read and subsequently transfer it to the memory being programmed. These data transfer operations create a time latency equal to the size of the sector divided by the flash memory interface bus width multiplied by the cycle time of the bus. Very often these operations are performed on the same physical memory device.
To further illustrate the impact these data transfer latencies have on the overall operation,
FIG. 1
is described here in more detail. Assume for the purposes of illustration that a block is comprised of sixteen sectors, each with incrementally assigned addresses sector 0 through sector 15, as shown in FIG.
1
. For the example where it is desired to rewrite new data in sector 7 through sector 9 of the data block, the write sequence is as follows:
1. Assign an unused, erased block (erase block 1) for the sector program operation;
2. Select address of the original block, read sector 0 of the original block, transfer data from flash EEPROM to controller;
3. Select address of the newly assigned block, transfer data back to flash EEPROM and program in sector 0 of the newly assigned block;
4. Repeat steps 2 and 3 for sectors 1 through 6;
5. Select address of the newly assigned block, transfer new host data for page 7 to flash EEPROM and program into sectors in the newly assigned block;
6. Repeat step 5 for sectors 8 and 9;
7. Select address of the original block, read sector 10 of the original block, transfer data from flash EEPROM to controller;
8. Select address of the newly assigned block, transfer data back to flash EEPROM and program into sector 10 of the newly assigned block;
9. Repeat steps 7 and 8 for sectors 11 through 15; and
10. Erase the original (now superseded) block for future write operations.
FIG. 2
shows a typical prior art flash EEPROM device's internal architecture
4000
. The key features include an I/O bus
411
and control signals
412
to interface to an external controller, a memory control circuit
450
to control internal memory operations with registers for command, address and status, one or more arrays
400
of flash EEPROM cells, each array with its own row decoder (XDEC)
401
and column decoder (YDEC)
402
, a group of sense amplifiers and program control circuitry (SA/PROG)
454
and a Data Register
404
.
If desired, a plurality of arrays
400
, together with related X decoders, Y decoders, program/verified circuitry, data registers, and the like is provided, for example as taught by U.S. Pat. No. 5,890,192; issued Mar. 30, 1999, and assigned to Sandisk Corporation, the assignee of this application, and which is hereby incorporated by reference.
The external interface I/O bus
411
and control signals
412
could be configured with the following signals:
CS—Chip Select. Used to active flash memory interface.
RS—Read Strobe. Used to indicate AD bus is being used for a data read operation.
WS—Write Strobe. Used to indicate AD bus is being used for a data write operation.
AS—Address Strobe. Indicates that AD bus is being used to transfer address information.
AD[7:0]—Address/Data Bus Used to transfer data between controller and flash memory command, address and data registers.
This interface is given only as an example, as other signal configurations can be used to give the same functionality. Although this diagram shows only one flash memory array
400
with its related components, it is understood that a multiplicity of arrays can exist on a single flash memory chip that share a common interface and memory control circuitry but have separate XDEC, YDEC, SA/PROG and DATA REG circuitry in order to allow parallel read and program operations.
Data from the EEPROM system
4000
data register
404
to an external controller via the data registers coupling to the I/O bus AD[7:0]
411
. The data register
404
is also coupled to the sense amplifier/programming circuit
454
. The number of elements of the data register coupled to each sense amplifier/programming circuit element may depend on the number of bits stored in each flash EEPROM cell. Each flash EEPROM cell may include a plurality of bits, such as 2 or 4, if multi-state memory cells are employed.
Row decoder
401
decodes row addresses for array
400
in order to select the physical sector being accessed. Row decoder
401
receives row addresses via internal row address lines
419
from memory control logic
450
. Column decoder
402
receives column addresses via internal column address lines
429
from memory control logic
450
.
It is common practice that each sector's worth of host data programmed into a sector is appended with an Error Detection and Correction code (ECC) that could be used to determine the validity of the stored data. Some such systems would use the occasion of the transfer as an opportunity to check the validity of the data being read as a way to ensure that the data would be correctly programmed in the new location. Due to the overall fidelity of these storage devices, the occurrence of failure during such verifications is rare.
FIG. 3
shows a typical flash card architecture that has a single controller
301
that performs host and memory control functions and a flash memory array that is composed of one or more flas
Conley Kevin M.
Gonzalez Carlos J.
Guterman Daniel C.
Caserza Steven F.
Flehr Hohbach Test Albritton & Herbert LLP
Le Vu A.
Nguyen Tuan T.
SanDisk Corporation
LandOfFree
Method and structure for reliable data copy operation for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for reliable data copy operation for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for reliable data copy operation for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2450164