Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-12-20
2001-11-20
Riley, Shawn (Department: 2838)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S787000
Reexamination Certificate
active
06320127
ABSTRACT:
TECHNICAL FIELD
The present invention relates to electronic semiconductor packages or assemblies incorporating flip-chip semiconductor devices, and more specifically to methods for underfilling such devices.
BACKGROUND OF THE INVENTION
Flip-chip semiconductor devices permit higher component density and faster access time than conventionally packaged semiconductor devices. These advantages have led to increased usage of such flip-chip devices in the electronic industry. A flip-chip semiconductor device is one in which a semiconductor chip (die) is directly mounted onto a packaging substrate, such as a ceramic or organic packaging substrate. Conductive terminals on an electrically active surface of the semiconductor die, usually in the form of conductive solder bumps, are directly contacted to the wiring patterns on the packaging substrate without the use of wire bonds, tape-automated bonding (TAB), or other like methods. Because the conductive bumps making the connections to the packaging substrate are on the active surface of the die or chip, the die is mounted in a face-down manner, thus the name flip-chip.
One problem in flip-chip mounting is that the coefficient of thermal expansion (CTE) of the die and that of the packaging substrate are frequently mismatched. For example, a silicon die has the CTE of about 3 parts per million per degree Celsius (ppm/° C.) while the CTE of a typical organic substrate is about 16 ppm/° C. and that of typical ceramic packaging substrate is about 6.5 ppm/° C. Since a die operating under normal operating conditions experiences significant variances in temperature, conductive bumps which couple the die to the packaging substrate are subjected to significant stress. This stress leads to thermal fatigue in the bumps and at the interfaces where the bumps contact the conductive bonding pads of a packaging substrate. This stress frequently leads to connection failures. A method used in the art for overcoming the difficulties inherent in the thermal mismatches between the die and substrate is to “underfill” the space between the die and the packaging substrate with an underfill material. This space between die and substrate is referred to as the underfill space. “Underfilling” is intended to fill all the space between the die and packaging substrate, as well as the space between the individual conductive bumps with underfill material (referred to alternatively as underfill or encapsulation material) forming an underfill layer. The effectiveness of the underfill material is achieved by mechanically coupling the die to the packaging substrate decreasing the stress at the die/substrate interface to improve the flip-chip device lifetime.
Although the use of underfill materials improves the reliability of flip-chip devices, the use of such materials create their own problems. One problem is that the process of underfilling sometimes creates voids in the area beneath the die. This occurs when the underfill material does not completely fill the space between the die and packaging substrate. The areas not filled are referred to as voids. When voiding occurs, conductive bumps located in the voided area undergo thermal fatigue as if no underfill material were present. Therefore, reducing the number and size of voids is a matter of serious concern.
Prevention of voids in underfill layer is governed by the properties of underfill materials, for example, rheology, viscosity, and filler content of the material. Additionally, the process of dispensing the material into the underfill space effects voiding as does the physical structure of the space to be underfilled.
Current processes align the die such that the conductive bumps are aligned with the conductive terminals (bonding pads) of the packaging substrate. After die alignment, the conductive bumps (typically formed of solder) are “melted” or reflowed to mechanically and electrically connect the die to the packaging substrate. The underfill space between the die and substrate are then underfilled. Underfill materials are typically injected along one or more of the four sides of the die. Current methods for applying underfill materials typically use a one- or two-sided dispensing process. This means that the underfill material is typically dispensed into the underfill space along only one or two sides of the die. Aided by capillary action, the underfill material propagates beneath the die, ostensibly filling all the space under the die and exiting on remaining sides. Ideally, such one- or two-sided processes push any air which is present in the underfill space out from under the die through the sides where the underfill material is not being applied.
FIG. 1
is a top perspective view of a typical die
10
as known in the art. The conductive solder bumps
11
are clearly shown. Although the die
10
is shown having conductive solder bumps
11
arranged in a specific configuration, the principles of the present invention may be applied to dies having conductive solder bumps in any configuration. The die
10
is typically flipped over and positioned such that the conductive solder bumps
11
are aligned with bonding pads of a packaging substrate (not shown). The solder bumps are then reflowed to bond them to the bonding pads of a packaging substrate. Then underfilling takes place.
The results of an exemplar one-sided underfill application are shown in
FIGS. 2-4
which are simplified top down views of a semiconductor die
10
and a packaging substrate
21
, undergoing an underfill process as known in the art. Initially, an underfill material
22
is dispensed along a first (or near) side
10
n
of the die
10
. Over time, the material
22
propagates across the die
10
in the direction indicated by the arrows of FIG.
2
. Unfortunately, the propagation pattern of the underfill material
22
across the die
10
is typically nonuniform, with the underfill material flowing across the surface at different rates. In many underfill processes the flow rates of the underfill material is greater along the edges of the die
10
(as indicated by the longer arrows) and slower near the center of the die
10
(indicated by the shorter arrows). This causes a non-linear flow pattern resulting in a so-called “concave flow front”
25
illustrated in FIG.
3
. As shown in
FIG. 4
, such concave flow fronts can lead to the formation of voids as the flow front coalesces around a second (or far) side
10
f
of the die
10
. The air entrapped in region
26
is difficult to remove, resulting in the subsequent formation of voids
26
in the underfill material
22
between the die
10
and the packaging substrate
21
.
These flow front problems are magnified in two-sided underfill processes or in die structures where the solder bump density is greater around the outer edges of the die (e.g.
FIG. 1
) leading to enhanced capillary flow of underfill material around the outer edges of the die
10
. Higher flow rates around the edges can also result from the effects of plasma or solvent cleaning of the die and packaging substrate.
One method of reducing the number of voids is to form a so-called “linear flow front” in the underfill material that does not demonstrate the concave geometry presently known in the art. What is needed is a electronic component package which demonstrates a reduced propensity for voiding in the underfill space between the die and packaging substrate. Also needed is a method for reducing the incidence of voids in the underfill space and a method for producing a flow front that does not demonstrate a concave flow front.
SUMMARY OF THE INVENTION
Accordingly, the principles of the present invention contemplate an electronic component structure having a packaging substrate with a top surface and a semiconductor die. The top surface of the packaging substrate including a plurality of bonding pads and a plurality of gutters formed thereon. The die, which includes conductive bumps on an electrically active surface thereof, is aligned and positioned such that the conductive bumps of the die are aligned with and electrically c
Nagarajan Kumar
Rajagopalan Sarathy
Fitch Even Tabin & Flannery
LSI Logic Corporation
Riley Shawn
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