Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-12-19
2002-08-20
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C029S832000, C361S734000, C361S767000
Reexamination Certificate
active
06437252
ABSTRACT:
PRIOR FOREIGN APPLICATION
This application claims priority from European patent application No. 99125462.4, filed Dec. 21, 1999, which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present invention relates in general to the reduction of power noise. In particular, it relates to such a reduction in the mid- and high-frequency range. Still more specifically, the invention relates to a pad-via configuration for SMT decoupling capacitors.
BACKGROUND ART
Due to the growing complexity of semiconductor devices the total amount of switching current needed by the logic devices increases. As a result the simultaneous switching noise increases also and results in a slower working logic, in a slower cycle time and thus in a decreasing system performance. In order to yield a higher system performance one goal of modern system designs is to stabilize the voltage. It is known that a stabilized voltage can be obtained with the help of decoupling capacitors mounted on MCMs, cards and boards. However, the higher power noise combined with a lower operating voltage of the semiconductor devices results in a growing number of capacitors needed for decoupling purposes. This results in additional problems:
large areas on MCM, cards and/or boards needed for capacitor placement and with a growing distance of the capacitor to the noise source the effectiveness of the capacitor is decreased
reduced placement area for capacitors, due to a higher component integration factor on cards/boards
growing costs for assembled components, due to a higher number of components and increase of manufacturing time (drilling of via holes, component placement, edging, etc.)
wiring problems on cards/boards, due to an increased number of power/ground vias as well as a possibly increased signal delay, decreased cycle time, increased number of card/board layers and decreased system performance
decreased effective copper on power and ground layers, due to an increased number of via and clearence holes; increased DC resistance of power and ground planes; increased DC voltage drop on card/board between voltage source and logic; decreased system performance.
In order to make all the capacitors as effective as possible the charge of the capacitors must be provided as fast as possible to the noise source. Therefore the internal inductance of the capacitor as well as the path inductance (capacitor to noise source) must be kept as small as possible. Due to these restrictions the capacitor must
be placed as close as possible to the noise source;
have a small internal inductance; and
have a small inductance of the capacitor pad and the via connecting the pad to the voltage and ground plane.
Decoupling capacitors are used to provide a short term current source or sink for the circuitry in an effort to provide a stable power supply. For example, the decoupling capacitors act as a storage device for electrical charge which can provide a short term current source for the circuitry.
It is well known in the art that capacitors with a low capacitance value may be used as a high frequency noise filter, and capacitors with a high capacity value may be used as a low frequency noise filter.
Typically, decoupling capacitors are placed as close as possible to the circuitry so as to increase their effectiveness. Thus, U.S. Pat No. 4,654,694 discloses side connections to place a capacitor in close proximity to a chip or, alternatively, to a chip and GND/Power I/O. By this technique, the effective inductance of the power paths is minimized.
In some instances, decoupling capacitors have been placed within the package containing the integrated circuit. Thus, U.S. Pat. No. 4,945,399 describes a semiconductor chip carrier including a plurality of distributed high frequency decoupling capacitors as an integral part of the carrier. The distributed capacitors are formed as a part of the first and second layers of metallurgy and separated by a layer of thin film dielectric material.
U.S. Pat. No. 5,132,613 discloses an integrated circuit test structure including individual layers of a personalization substrate and decoupling capacitors, whereby said decoupling capacitors are electrically coupled to the metal lines in close proximity, the personalization substrate thereby minimizing the associated lead inductance and thus maximizing the effectiveness of the decoupling capacitors.
Although there are some advantages in using capacitors with a low internal inductance, a great disadvantage is the also low capacitance of the capacitor itself (low inductance is only available with low capacitance). One further disadvantage is the decreased effectiveness of the low inductive capacitor that is limited by the inductance of the mounting pads together with the vias of the capacitor.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of several surface mount decoupling capacitors, whereby the parasitic inductance of the pads and vias is minimized.
It is a further object of the present invention to increase the effectiveness of the decoupling capacitors, to reduce the voltage drop and to increase the overall system performance.
These and other objects and advantages are achieved by a method for minimizing switching noise in the high- and mid-frequency range according to aspects of the present invention.
Advantageous embodiments of the method according to the invention are laid down in the claims.
REFERENCES:
patent: 5949657 (1999-09-01), Karabatsos
patent: 6043987 (2000-03-01), Goodwin et al.
patent: 6198362 (2001-03-01), Harada et al.
patent: 6330164 (2001-12-01), Khandros et al.
Becker Wiren
Chamberlin Bruce
Frech Roland
Klink Erich
Ma Wai
Augspurger, Esq. Lynn L.
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Paladini Albert W.
Radigan, Esq. Kevin P.
LandOfFree
Method and structure for reducing power noise does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for reducing power noise, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for reducing power noise will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2899762