Method and structure for providing ESD protection for silicon on

Details Method and structure for providing ESD protection for silicon on Method and structure for providing ESD protection for silicon on

1995-01-20

1997-03-11

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, H02H 900

Patent

active

056107900

ABSTRACT:
A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.

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