Method and structure for prevention leakage of substrate strip

Details Method and structure for prevention leakage of substrate strip Method and structure for prevention leakage of substrate strip

2006-08-15

2006-08-15

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257SE21504, C257SE23002, C257SE23069

Reexamination Certificate

active

07091583

ABSTRACT:
The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer. By removing the exposed portion of the plating bus, the breaking hole is formed to electrically isolate the extended trail from the contact pads in order to prevent a chip on the substrate strip from being damaged by ESD (Electrostatic Discharge) during packaging processes.

REFERENCES:
patent: 6723583 (2004-04-01), Takahashi et al.
patent: 508769 (2002-10-01), None

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