Method and structure for optimizing the performance of a semicon

Details Method and structure for optimizing the performance of a semicon Method and structure for optimizing the performance of a semicon

1997-10-31

1999-10-19

Dutton, Brian

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438 18, 324765, H01L 2100, H01L 2166, G01R 3126

Patent

active

059703113

ABSTRACT:
A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.

REFERENCES:
patent: 5304925 (1994-04-01), Ebina
patent: 5598010 (1997-01-01), Uematsu
patent: 5760600 (1998-06-01), Kasai

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