Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
1999-05-20
2001-01-23
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
Reexamination Certificate
active
06177293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to CMOS image sensors. More specifically, the present invention relates to a method and pixel structure designed to reduce excess leakage currents, and to a method for fabricating CMOS image sensors that generate images that are free of white spots.
RELATED ART
Solid state image sensors used in, for example, video cameras are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a display.
CMOS image sensors first appeared in 1967. However, CCDs have prevailed since their invention in 1970. Both solid-state imaging sensors depend on the photovoltaic response that results when silicon is exposed to light. Photons in the visible and near-IR regions of the spectrum have sufficient energy to break covalent bonds in silicon. The number of electrons released is proportional to the light intensity. Even though both technologies use the same physical properties, all-analog CCDs dominate vision applications because of their superior dynamic range, low fixed-pattern noise (FPN), and high sensitivity to light.
More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography, coupled with advanced signal-processing algorithms, sets the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array. This reduction of metal-line widths exposes more silicon to light, thereby increasing light sensitivity. CMOS image sensors also provide greater power savings, because they require fewer power-supply voltages than do CCD imagers. In addition, due to modifications to CMOS pixels, newly developed CMOS image sensors provide high-resolution, low-noise images that compare with CCD imager quality.
CMOS pixel arrays are at the heart of the newly developed CMOS image sensors. CMOS pixel-array construction uses active or passive pixels. Active-pixel sensors (APSs) include amplification circuitry in each pixel. Passive pixels use photodiodes to collect the photocharge, whereas active pixels can include either photodiode or photogate light sensitive regions.
The first image-sensor devices used in the 1960s were passive pixel arrays. Each pixel of a passive pixel array includes a photodiode for converting photon energy to free electrons, and an access transistor for selectively connecting the photodiode to a column bus. After photocharge integration in the photodiode, an array controller turns on the access transistor. The charge stored in the photodiode transfers to the capacitance of the column bus, where a charge-integrating amplifier at the end of the bus senses the resulting voltage. The column bus voltage resets the photodiode, and the controller then turns off the access transistor. The pixel is then ready for another integration period.
Shortcomings still plague passive pixel arrays. The read noise for passive pixels is high, and it is difficult to increase the array's size without exacerbating the noise. Ideally, the sense amplifier at the bottom of the column bus senses each pixels charge equally, independent of the pixel's position on the bus. Realistically, low charge levels from remotely-located pixels provide insufficient energy to charge the distributed capacitance of the column bus. Matching access transistors is also a problem. The turn-on thresholds for the access transistors vary throughout the array, giving non-uniform response to identical light levels. These threshold variations are one cause of FPN.
CMOS active-pixel sensors (APSs) overcome passive-pixel deficiencies by including active circuits (transistors) in each pixel. One type of an active circuit includes a source-follower transistor, a reset transistor and a row-selection transistor. The source-follower transistor buffers the charge transferred to an output (column) bus from the light sensing element (i.e., photodiode or photogate), and provides current to charge and discharge the bus capacitance more quickly. The faster charging and discharging allow the bus length to increase. This increased bus length, in turn, allows an increase in the array size. The reset transistor controls integration time and, therefore, provides for electronic shutter control. The row-select transistor gives half the coordinate-readout capability to the array. Although these transistors would appear to increase the device's power consumption, little difference exists between an active and a passive pixel's power consumption.
A problem associated with CMOS APSs is that adding these active circuits to each pixel reduces the fill factor (i.e., the ratio of light sensing area to total pixel area) of CMOS APS pixel arrays. In response, APS designers have modified the pixel shape to maximize the light sensing area. However, CMOS APS pixel arrays incorporating these modifications often experience white spots in the image generated by a CMOS APS.
What is needed is a method for fabricating pixel sensor structures that minimizes the occurrence of white spots on images produced by CMOS image sensors.
SUMMARY
The present inventors have determined that a significant cause of white spot problems in CMOS image sensors is excessive current leakage from the light-sensitive (e.g., photodiode) regions. In particular, this excessive current leakage appears to occur in regions that are subjected to excessive mechanical stress during fabrication, and to regions that are subjected to excessive electrical stress during device operation.
Accordingly, the present invention provides structures and methods for producing CMOS image sensors that minimize mechanical and electrical stress in the field oxide surrounding the light sensitive regions of the pixels, thereby reducing leakage current and minimizing white spots in the CMOS image sensor.
In accordance with a first aspect of the present invention, the field oxide surrounding the light sensitive region of each pixel is formed with interior angles greater than 90° (with rounded corners), and more preferably with interior angles of 135° or greater. In one embodiment, the field oxide surrounding the light sensitive region is continuously curved. By increasing these interior angles, high stress regions typically created by the localized growth of field oxide at the field oxide/light sensitive region interface is minimized, thereby minimizing leakage current from the light sensitive region.
In accordance with a second aspect of the present invention, the polysilicon structure used to form, for example, the reset transistor gate of each pixel is offset from the light sensitive region by a distance greater than 0.25 &mgr;m. The gate structures are typically formed using a plasma etching process. By spacing the gate structures away from the light sensitive region, high stress regions in the field oxide that are typically created during the etching process are minimized. In addition, the electrical field between the light sensitive region and the polysilicon gate of, for example, the reset transistor is reduced. Thus, leakage current from the light sensitive region is minimized.
In accordance with a third aspect of the present invention, a mask is provided over the interface between the field oxide and the light sensitive region during lightly-doped drain (LDD) sidewall spacer formation (etch-back). These LDD spa
Koltin Ephie
Netzer Yossi
Rotstein Israel
Bever Patrick T.
Bever Hoffman & Harms LLP
Bowers Charles
Pert Evan
Tower Semiconductor Ltd.
LandOfFree
Method and structure for minimizing white spots in CMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for minimizing white spots in CMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for minimizing white spots in CMOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470956