Method and structure for making self-aligned contacts

Details Method and structure for making self-aligned contacts Method and structure for making self-aligned contacts

1999-06-04

2001-04-10

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S738000, C438S743000

Reexamination Certificate

active

06214743

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly the formation of contacts holes and/or contact structures in a semiconductor device.
BACKGROUND OF THE INVENTION
Integrated circuits can typically include various layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Such active devices may then be connected to one another by one or more conductive or semiconductive layers. The interconnecting conducting layers may be separated from one another by insulating layers.
Insulating layers typically provide electrical isolation between conductive layers. While insulating layers can be formed from a variety of materials, one consideration in selecting an insulating material can be the dielectric constant of the material. If a high dielectric constant material isolates a conductive line from a substrate, “parasitic” capacitance and/or transistor effects can occur.
Conductive or semiconductive layers may be formed from a single layer of material, or alternatively, include one or more conductive (or semiconductive) materials. As just a few examples, such a layer can include a conventionally doped polycrystalline silicon (polysilicon) and “silicide” (silicon-metal alloy). Alternatively, a conducting layer can include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TIN), or a Ti alloy. Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a “doped” silicon dioxide (“oxide”) and an “undoped” silicon oxide (undoped silicate glass or “USG”). The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide will be essentially free of dopant elements. Phosphorous doped silicon dioxide (phosphosilicate glass or “PSG”) can provide advantageous ion gettering and step coverage properties. Boron and phosphorous doped silicon dioxide (borophosphosilicate glass or “BPSG”) can also provide such advantages, and can be formed at lower temperatures.
Different conductive or semiconductive layers can be connected to one another by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, contacts can connect a substrate to a conductive or semiconductive layer, while a via can connect two different conductive or semiconductive layers to one another.
A conventional way of forming a contact hole in one or more insulating layers can include lithography and etch steps. Lithography can be used to form a pattern over an insulating layer (that includes the location of contact holes). An etch step can transfer the pattern onto the insulating layer.
One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conductive or semiconductive, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. Further, it may be desirable to ensure that a contact hole can be sufficiently insulated from other conductive lines. For example, in the case of semiconductor devices having insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor FETs (MOSFETs), it is desirable to have a contact hole aligned with a source or drain, but at the same time, be sufficiently insulated from a gate conductor.
Another concern regarding contacts and/or vias can be the area of the contact. The area of a contact can be of concern as a substrate on which a contact is formed can also include other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or device wells. Thus, reductions in contact size can provide more area for other features and/or reduce the overall size of an integrated circuit device. Further, in many processes contact area may have a minimum requirement in order to ensure a low enough contact resistance value. Thus, it is desirable that a contact forming process be capable of meeting a minimum contact resistance value.
Various factors may contribute to reducing contact area. One such factor is that of contact aspect ratio (AR). An aspect ratio can describe the ratio between a contact height and width, when viewed in cross section. The higher the aspect ratio, the more difficult it may be to form the contact.
To better understand the formation of certain integrated circuit structures, including contacts and contact holes, a conventional self-aligned contact (SAC) approach is set forth in FIGS.
5
and
6
A-
6
G.
FIG. 5
is a flowchart illustrating the general steps involved in forming a self-aligned contact for an integrated circuit that includes MOSFETs.
FIGS. 6A-6G
set forth a number of side cross-sectional views of a portion of an integrated circuit following the various steps described in FIG.
5
.
The conventional process set forth in
FIG. 5
is designated by the general reference character
500
. The process
500
can begin by forming MOSFET gate stacks having sidewalls (step
502
). A portion of an integrated circuit following step
502
is set forth in
FIG. 6A. A
MOSFET gate stack
600
can be formed on a substrate
602
, and include a gate oxide
604
, conductive portions
606
, and an insulating portion
608
. Sidewalls
610
are also set forth in FIG.
6
A.
It is noted that a substrate
602
can include isolation structures formed therein by a previous substrate isolation structure forming step. As just two examples, a substrate
602
can include shallow trench isolation structures and/or local oxidation of silicon (LOCOS) structures. Further, a substrate
602
may also include doped portions formed with previous and/or subsequent doping steps, such as transistor sources, drains, channels, and device wells.
A conventional process
500
can continue with the deposition of an insulating layer of BPSG and USG (step
504
). A portion of an integrated circuit following step
504
is set forth in FIG.
6
B. Referring now to
FIG. 6B
, the integrated circuit portion includes a BPSG layer
612
and an USG layer
614
formed over the BPSG layer
612
. The BPSG and USG layers (
612
and
614
) may be formed over MOSFET gate stacks
600
and may be deposited using chemical vapor deposition (CVD) methods.
The conventional process
500
can continue with lithography and etch steps. A photoresist layer can be deposited on a USG layer
614
(step
506
). Referring to
FIG. 6C
, an example of a portion of semiconductor device following a step
506
is shown in a side cross sectional view. A photoresist layer (“resist”) can include a photoresist material
616
and a bottom antireflective coating (BARC)
618
.
The photoresist material
616
can be patterned (step
508
). Typically, a photoresist material
616
can be patterned by selectively exposing portions of the photoresist material to a radiation source. Typically a photomask can be used to establish the pattern. Radiation sources can include various light sources, including coherent light, from various spectrums including the visible spectrum and ultraviolet spectrum. Other methods can utilize X-rays, electron beam (e-beam), or ion beams to form a pattern in a photoresist material
616
, to name but a few examples. E-beam and ion beam systems may not require a photomask.
A BARC
618
can reduce deleterious “corner” effects and/or other undesirable developing artifacts that may occur with smaller geometry devices.
Portions of the photoresist material
616
can then be removed according the pattern developed by the exposure to radiation. A portion of a semiconductor device after removal of photoresist material is shown in FIG.
6
D. Once selected portions of the photoresist material
616
are removed, the photoresist mater

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