Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Low workfunction layer for electron emission
Reexamination Certificate
2000-10-05
2003-01-21
Abraham, Fetsum (Department: 2820)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Low workfunction layer for electron emission
C257S144000, C257S163000
Reexamination Certificate
active
06509578
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to field emission devices.
A field emission display (FED) has a cathode with a selectable array of thin film emitters, and a phosphor coated anode, as shown, for example, in U.S. Pat. No. 5,210,472, which is assigned to the same assignee and is incorporated by reference for all purposes. The emitters are typically sharp pointed cones formed over a conductive layer. These emitters emit electrons in the presence of an intense electric field between an extraction grid over the emitters and the conductive layer. The electrons bombard the anode to provide a light image that can be viewed. By selecting desired emitters and controlling the charge delivered to the phosphor in a given pixel, the brightness of the pixel can be varied. The change in brightness is generally proportional to the increase in the delivered charge.
As current from the emitter increases, resistance decreases, thus increasing the current and resulting in a runaway condition. To avoid this problem, continuous current-limiting resistive layers were provided between emitters and conductive layers in “Current Limiting of Field Emitter Array Cathodes,” a thesis by K. Lee at the Georgia Institute of Technology, August, 1986; and Borel, U.S. Pat. No. 4,940,916. Such current-limiting resistors in series with the emitters have several drawbacks: they can short during operation; other defects can occur during processing, thus resulting in inoperable cathode emitters; and if a number of tips fail, the current can still exceed thresholds.
SUMMARY OF THE INVENTION
According to the present invention, current is limited in FED emitters by controllably implanting ions in a silicon layer to produce a desired maximum current in the resulting emitter tips. The implanted ions are diffused downwardly by heating after the implantation step, or upwardly by forming an epitaxial layer over the silicon layer. A next implantation step provides a more heavily doped n-type region where the tips of the emitters will be formed to reduce the work function. The emitter itself is thus current-limited and does not need an additional resistive layer in series.
The present invention removes from the fabrication process relative nonuniform steps of forming resistors and substitutes one or more highly controllable ion implantation steps. The present invention limits current while avoiding the need for a separate layer of resistive material in series with the emitters. Other features and advantages will become apparent from the following detailed description, drawings, and claims.
REFERENCES:
patent: 4766340 (1988-08-01), van der Mast et al.
patent: 4940916 (1990-07-01), Borel et al.
patent: 5210472 (1993-05-01), Casper et al.
patent: 5229331 (1993-07-01), Doan et al.
patent: 5354694 (1994-10-01), Field et al.
patent: 5372973 (1994-12-01), Doan et al.
patent: 5420054 (1995-05-01), Choi et al.
patent: 5532177 (1996-07-01), Cathey
patent: 5710478 (1998-01-01), Kanemaru et al.
patent: 5818153 (1998-10-01), Allen
Abraham Fetsum
Hale and Dorr LLP
Micro)n Technology, Inc.
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