Method and structure for improving the linearity of MOS...

Details Method and structure for improving the linearity of MOS... Method and structure for improving the linearity of MOS...

2005-05-24

2005-05-24

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S530000

Reexamination Certificate

active

06897701

ABSTRACT:
A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

REFERENCES:
patent: 5689209 (1997-11-01), Williams et al.
patent: 5880620 (1999-03-01), Gitlin et al.
patent: 6064262 (2000-05-01), Wang
patent: 6628159 (2003-09-01), Voldman
patent: 6661277 (2003-12-01), Dabral

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