Method and structure for implementing dynamic chip burn-in

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

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174254, 174260, 174268, 357 69, 357 70, 361400, 361409, 361412, H05K 100

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active

051648881

ABSTRACT:
A method and structure for implementing dynamic burn-in of semi-conductor chips in TAB processing is provided. The semi-conductor chips are mounted on a wire pattern formed on the obverse side of an insulating tape in a conventional way. The insulating tape has a plurality of openings extending therethrough, one opening between each adjacent location of a chip. Wires from the wiring pattern at each chip location pass over the openings on the obverse side of the tape. A second insulating tape is provided which has a series of parallel conductors formed on one surface thereof. The spacing of the conductors corresponds to the spacing of the wires over the openings.
The second tape is applied to the reverse surface of the first tape with the conductors on the second tape in registration with the wires over the openings in the first tape and the wires are electrically bonded to the conductors. Thus, various voltage and signal levels can be supplied for all of the chips simultaneously during dynamic burn-in.

REFERENCES:
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patent: 3818279 (1974-06-01), Seeger et al.
patent: 4386389 (1983-05-01), Proebsting
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patent: 4701781 (1987-10-01), Sankhagowit
patent: 4981817 (1991-01-01), Stone, Jr.
patent: 5028983 (1991-07-01), Bickford et al.
IBM Technical Disclosure Bulletin "Burn-in Methodology for Tab Using Separate Signal Carrier Tape" vol. 32 No. 1 Jun. 1989.

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