Method and structure for generating a boosted word line voltage

Details Method and structure for generating a boosted word line voltage Method and structure for generating a boosted word line voltage

1996-02-29

1997-12-30

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518909, 36518911, 365149, G11C 700

Patent

active

057038279

ABSTRACT:
A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V.sub.CC supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.

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