Method and structure for enhancing the access time of integrated

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365203, 36518911, G11C 700

Patent

active

059462647

ABSTRACT:
A memory structure features a write driver circuit that is controlled to assist equilibrate devices recover one or more bitlines attached to a memory cell following the completion of a write operation of the memory cell. After the write operation, a write bus true and a write bus complement generated by the write driver are coupled to bitlines and equilibration devices by passgates controlled by a control signal.

REFERENCES:
patent: 5784329 (1998-07-01), Blankenship et al.
patent: 5805515 (1998-09-01), Suzuki
patent: 5867437 (1999-02-01), Massoumi et al.

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