Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2002-07-02
2004-08-17
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S136000, C257S217000, C257S256000, C257S268000, C257S272000, C257S283000, C257S504000
Reexamination Certificate
active
06777722
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention relate to the field of junction field effect transistors (JFETs). More particularly, embodiments of the present invention relate to a reduction in the input capacitance of JFETs.
BACKGROUND ART
Junction field effect transistors (JFETs) are majority carrier devices that conduct current through a channel that is controlled by the application of a voltage to a p-n junction. JFETs may be constructed as p-channel or n-channel and may be operated as enhancement mode devices or depletion mode devices.
The most common JFET type is the depletion mode type. The depletion mode device is a normally “on” device that is turned off by reverse biasing the p-n junction so that pinch-off occurs in the conduction channel. P-channel depletion mode devices are turned off by the application of a positive voltage between the gate and source (positive V
gs
), whereas n-channel depletion mode devices are turned off by the application of a negative voltage between the gate and source (negative V
gs
). Since the junction of a depletion mode JFET is reverse biased in normal operation, the input voltage can be relatively high. Devices are available with input voltages with a magnitude greater than 100 volts.
Enhancement mode, or normally “off” JFETs are characterized by a channel that is sufficiently narrow such that a depletion region at zero applied voltage extends across the entire width of the channel. Application of a forward bias reduces the width of the depletion region in the channel, thereby creating a conduction path in the channel. P-channel enhancement mode JFETs are turned on by the application of a negative V
gs
, and n-channel enhancement mode JFETs are turned on by the application of a positive V
gs
. The input voltage of an enhancement mode JFET is limited by the forward breakdown voltage of the p-n junction.
The capacitance of a gate structure and its variation with voltage is related to the doping profile of the gate structure. Control over the doping profile can lessen the voltage dependence of the interelectrode capacitance and improve the output characteristics for analog applications such as amplifiers. The doping of the gate region of a JFET by ion implant has traditionally allowed for a degree of control over the doping profile in the direction normal to the substrate surface by varying acceleration potential applied to the ions being implanted. However, the prior art has not provided an equivalent degree of control over the lateral dopant distribution.
Historically, JFETs have been used for analog switches, radio frequency devices, current regulators and high input impedance amplifiers, while logic circuits such as microprocessors have been the domain of metal oxide semiconductor field effect transistors (MOSFETs) as exemplified by complementary metal oxide semiconductor (CMOS) technology.
Traditionally, JFETs have been used as discrete devices or as input stages on integrated circuits such as operational amplifiers. However, as circuit complexity, operating frequency, and power management requirements have increased for CMOS devices such as microprocessors, it has become desirable to integrate power management and conditioning functions on the same die with the logic. JFETs are candidates for performing these functions
A transistor structure that is integrated on a logic circuit for the purpose of power management and conditioning will be faced with a requirement for high frequency operation and low power consumption. For field effect transistors (FETs), parasitic capacitances between the gate and source (C
gs
) and gate and drain (C
gd
) are significant factors affecting performance in this regard. In general, a low gate capacitance is desirable for transistors used in both analog and digital circuits. A low capacitance provides faster switching, higher frequency response and lower current and power requirements.
Although the characteristics of JFETs qualify them as candidates for integration with high speed logic circuits having sophisticated power management requirements, the conventional JFET device structures and processes are not optimized for such integration. The structures and processes that have heretofore been used to produce discrete devices or analog integrated circuits were not designed for integration with CMOS structures and processes.
SUMMARY OF INVENTION
Thus, a need exists for a JFET with minimal parasitic capacitances C
gs
and C
gd
. There is also a need for method for producing an optimal JFET structure that is compatible with the process flow used for logic integrated circuits. Additionally there is a need for increased flexibility in the control of the lateral doping profile in a gate structure.
Accordingly, embodiments of the present invention include a JFET structure that has reduced C
gs
and C
gd
and provides improved performance at high frequencies and greater power efficiency. Another aspect of the invention is a fabrication method that is readily integrated with a conventional process flow for logic integrated circuits. These and other objects and advantages of the present invention and others not specifically recited above will be described in more detail herein.
In an embodiment of the present invention, a gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to controlling the final junction geometry and thereby reducing the junction capacitance by establishing the lateral extent of the implanted gate region, the gate definition spacer also limits the available diffusion paths for the implanted dopant species during anneal. The net result is that the interfacial area between the gate and source and gate and drain are reduced, thereby reducing the associated parasitic capacitances C
gs
and C
gd
.
In another embodiment of the present invention, a gate region is formed by implanting and annealing. After annealing, a portion of the gate structure that is not directly adjacent to the channel is removed, thereby decreasing the parasitic capacitance C
gd
between the gate and drain.
In a further embodiment of the present invention two ion implant steps are performed over different but overlapping volumes in order to provide an additional degree of flexibility in controlling doping profile of the gate region. By using a “double dose” process comprising a low dose for the first implant over a larger volume followed by a high dose implant over a smaller volume, a graded junction is obtained.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
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Liva Valentino L.
Pegler Pete
Yu Ho-Yuan
Huynh Andy
Lovoltech Inc.
Nelms David
Wagner , Murabito & Hao LLP
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