Method and structure for digital phase synchronization

Details Method and structure for digital phase synchronization Method and structure for digital phase synchronization

1989-10-23

1991-06-04

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

370108, 328 72, H03D 324

Patent

active

050220560

ABSTRACT:
A novel method and structure is taught for synchronizing a received digital data stream to the receiver clock. A plurality of delay lines; are used to provide a plurality of delayed input signals, which are then compared with the receiver clock signal in order to determine which of the delayed input signals is closest in phase to the receiver clock signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed input signals for use by the receiver. In an alternative embodiment, a plurality of delay lines are used to provide a plurality of delayed clock signals, which are then compared with the receiver input signal in order to determine which of the delayed clock signals is closest in phase to the receiver input signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed clock signals for use by the receiver.

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"Advanced Peripherals", Mass Storage Handbook, 1988 Edition, Rev. 2.

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