Method and structure for data traffic reduction for display refr

Details Method and structure for data traffic reduction for display refr Method and structure for data traffic reduction for display refr

1995-07-12

1999-08-17

Hjerpe, Richard A.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345511, 345203, 345512, G09G 500

Patent

active

059400889

ABSTRACT:
A method and structure for performing a screen refresh operation in a video processing system which includes a frame buffer memory and a display controller coupled to a system bus. A status bit memory is used to store status bits which represent the repetitive characteristics of pixel data stored in the frame buffer memory. The status bits are provided to the display controller. In response, the display controller determines whether to provide pixel data by regenerating pixel data previously retrieved from the frame buffer memory or by accessing the frame buffer memory.

REFERENCES:
patent: 5473764 (1995-12-01), Chi
patent: 5526025 (1996-06-01), Selwan et al.

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