Method and structure for creating a self-aligned bicmos-compatib

Details Method and structure for creating a self-aligned bicmos-compatib Method and structure for creating a self-aligned bicmos-compatib

1993-06-23

1995-08-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 33, 437 41, 437 44, 437 59, 437162, H01L 21265, H01L 2170, H01L 2700, H01L 21255

Patent

active

054440033

ABSTRACT:
A bipolar transistor is fabricated in a CMOS-compatible process so as to be self-aligning, with resultant small geometry and improved high frequency performance, and to have improved hot carrier characteristics. The bipolar device has a laterally graded emitter structure that is fabricated in a "top-down" implant process. During fabrication sidewall spacers are formed overlying the peripheral region of the laterally graded emitter. These spacers protect the underlying region against counter-doping during a subsequent intrinsic base implant, and cause the emitter and base contacts to be self-aligning. Because bipolar dimensions are thus reduced, a very narrow base width is achieved, resulting in improved device cutoff frequency. Further, a narrower emitter-base contact separation is achieved, reducing junction area and attendant junction capacitance. A base link region is formed to further improve emitter-base breakdown voltage, and to reduce extrinsic base resistance. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity. BiCMOS fabrication can occur wherein substantially the same process steps are employed, or wherein specific bipolar and MOS implant steps are decoupled to optimize laterally graded emitter dopant profiles, base-link resistance, and MOS off-state leakage currents.

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Stanley Wolf and Richard N. Tauber "Silicon Processing for the VLSI Era"280-282, 311-314 (1986).

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