Method and structure for controlling internal operations of a DR

Details Method and structure for controlling internal operations of a DR Method and structure for controlling internal operations of a DR

1995-08-31

1997-03-25

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365201, 365207, 365190, G11C 700

Patent

active

056151691

ABSTRACT:
A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a rising edge of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before the falling edge of the clock signal occurs. The falling edge is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before the subsequent rising edge of the clock signal. The subsequent rising edge is then used to initiate the column address decoding operation of the DRAM array. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.

REFERENCES:
patent: 4924443 (1990-05-01), Mattausch
patent: 5029135 (1991-07-01), Okubo
patent: 5287327 (1994-02-01), Takasugi

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