Method and structure for controlling internal operations of a DR

Details Method and structure for controlling internal operations of a DR Method and structure for controlling internal operations of a DR

1996-11-27

1998-01-13

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365201, 36518901, G11C 700

Patent

active

057086249

ABSTRACT:
A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and/or falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a first transition of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before a second transition of the clock signal occurs. The second transition is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before a third transition of the clock signal. The third transition of the clock signal is then used to initiate the column address decoding operation of the DRAM array. In an alternative embodiment, the column address decoding is initiated when a column access (CAS#) signal is asserted and the clock signal undergoes the third transition. The first, second and third transitions can be consecutive or non-consecutive edges of the clock signal. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.

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"Dynamic Clock Frequency Changing for a Memory Controller", IBM Technical Disclosure Bulletin, vol. 32, No. 9A, Feb. 1990, New York, pp. 345-350, XP000083101.
Preliminary Data Sheet, KM741006J CMOS SRAM, "262,144 Words.times.x 4-Bit Synchronous Static Random Access Memory," Samsung Electronics, pp. 348-354 (date and author unknown).

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