Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-08-18
2004-04-13
Vu, Ngoc-Yen (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S230100, C348S315000, C358S483000
Reexamination Certificate
active
06721010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and structure of accelerating image-sensing speed in a CCD image-sensing device.
2. Description of the Related Art
CCD image-sensing devices are widely applied in image processing systems and digital signal processing systems where they serve as shift registers or sequential memory devices with high density. For example, CCD image-sensing devices are utilized in scanners, digital cameras and copy machines.
For conventional scanners or contact image scanners, image processing components are comprised of CCD image-sensing devices.
FIG. 1
shows the schematic structure of a conventional CCD image-sensing device. In general, a CCD image-sensing device is composed of the following: a row of image-sensing elements (P
1
~P
n
) for sensing light energy and generating charge packets proportional to the light intensity; a CCD analog shift register
10
with multiple register elements (SH
1
~SH
2n
) for receiving and registering (storing) charge packets in parallel; a plurality of shift-control electrodes (G
1
~G
2n
); and an output amplifier (OP) for converting each of the charge packets into proportional voltage level(s) (V
im
). The CCD shift register
10
is controlled by two clock signals, &PHgr;
1
and &PHgr;
2
, which serially shift the charge packets stored in the register elements to the output amplifier (OP).
FIGS.
2
(
a
) to
2
(
e
) show the charge transferring process in the traditional CCD shift register depicted in FIG.
1
. FIG.
2
(
f
) shows the waveforms of the clock signals &PHgr;
1
and &PHgr;
2
. The clock signals &PHgr;
1
and &PHgr;
2
are coupled to shift-control electrodes G
2a
, and G
2a−1
(1≦a≦n) respectively.
FIG.
2
(
a
) schematically depicts the structure of CCD shift register
10
. For brevity, only 5 shift-control electrodes (G
1
~G
5
) are shown in the CCD shift register and the threshold voltage is displayed as 0. The 5 shift-control electrodes (G
1
~G
5
), and the p-type semiconductor substrate (hereinafter referred to as p-type substrate or P
sub
) together form
5
register elements (SH
1
~SH
5
).
FIG.
2
(
b
) depicts the distribution of potential barriers (step barriers) in the p-type substrate P
sub
when at time t
1
, &PHgr;
1
and &PHgr;
2
are at voltage levels
0
and V respectively. The potential barriers beneath shift-control electrodes G
1
, G
3
, and G
5
are higher than those beneath shift-control electrodes G
2
and G
4
. Hence, the charge packets (depicted as dashed lines) will be stored in the regions beneath the shift-control electrodes G
2
and G
4
in the p-type substrate P
sub
(i.e., register elements SH
2
and SH
4
).
FIG.
2
(
c
) depicts the distribution of potential barriers in the p-type substrate P
sub
when at time t
2
, both &PHgr;
1
and &PHgr;
2
are at voltage levels V/2. The arrows in FIG.
2
(
c
) demonstrate that when time changes from t
2
to t
3
, the potential barriers beneath the odd numbered shift-control electrodes will decrease and those beneath even numbered shift-control electrodes will increase.
FIG.
2
(
d
) depicts the distribution of potential barriers in the p-type substrate P
sub
when at time t
3
, &PHgr;
1
and &PHgr;
2
are at voltage levels 3V/4 and V/4 respectively. Hence, the charge packets stored beneath the register elements SH
2
and SH
4
are transferred to the regions beneath the shift-control electrodes G
1
and G
3
with lower potential barriers (i.e., register elements SH
1
and SH
3
).
Lastly, FIG.
2
(
e
) depicts the distribution of potential barriers in the p-type substrate P
sub
when at time t
4
, &PHgr;
1
and &PHgr;
2
are at voltage levels V and
0
respectively. During the period measured from t
1
to t
4
, the charge packets are transferred one register element to the right. Similarly, during the periods from t
5
to t
6
and t
7
to t
8
, the charge packets are also transferred one register element to the right.
The resolution of scanners generally is 600 dpi (dots per inch) or more. When a scanner with 600 dpi resolution scans a document of A
4
size (width=21 cm, length=29.7 cm), the CCD image-sensing device used by the scanner must be comprised of at least 7016 (≅29.7 cm/2.54 cm×600) image-sensing elements and 14032 (7016×2) register elements in order to receive and register the charge packets corresponding to the image(s) within the scanned document.
Vendors of CCD image-sensing devices generally provide standard products having more than 10000 image-sensing elements. For example, standard CCD image-sensing devices have 12800 image-sensing elements (P
1
~P
12800
) and 25600 register elements (SH
1
~SH
25600
). When the standard CCD image-sensing product applies a resolution of 600 dpi to an A
4
sized document, only 14032 register elements (SH
1
~SH
14032
) actually receive and register charge packets corresponding to the image(s) of the scanned document. The charge packets in register elements (SH
14033
~SH
25600
) are generated by light leakage or some other disturbance and do not correspond to the image(s) of the scanned document. Therefore, the charge packets registered in register elements (SH
14033
~SH
25600
) are undesired and redundant. Yet inevitably, redundant charge packets appear in every image-sensing operation.
According to the descriptions in FIGS.
2
(
a
) to
2
(
e
), the charge packets are serially shifted out of the CCD shift register and transformed to corresponding voltage levels. After shifting out the charge packets registered in register elements (SH
1
~SH
14032
), the charge packets registered in register elements (SH
14033
~SH
256000
) are also serially shifted for a displacement of 14032 register elements, netting 11,568 redundant charge packets stored in register elements (SH
1
~SH
11568
). In order for the CCD image-sensing device to carry out further image-sensing operations, the redundant charge packets must be serially shifting out of register elements (SH
1
~SH
11568
). Otherwise, the remaining (redundant) 11568 charge packets will be added to the newly received 11568 charge packets (from the next scanned image within the document). If not previously disposed of, these remaining, redundant charge packets will cause subsequent scanned image(s) to be distorted. Therefore, to avoid disturbance of the 11568 remaining, desired charge packets, the current art requires additional processing time to serially shift the 11568 remaining charge packets out of the CCD shift register before the CCD image-sensing device carries out its next image-sensing operation. Of course, this additional operation slows down the overall scanning and processing speed(s) of the scanner.
Presently, one method is widely applied in the industry to reduce the additional time required for processing of the remaining charge packets. This method involves increasing the frequency of clock signals &PHgr;
1
and &PHgr;
2
when shifting out the remaining charge packets as a means to accelerate the shift operation of the remaining charge packets thereby reducing additional processing time. Clock signals &PHgr;
1
and &PHgr;
2
generally operate at a normal frequency to shift out the desired charge packets (registered in the register elements Sh
1
~SH
14032
). However, clock signals &PHgr;
1
and &PHgr;
2
must operate at increasingly higher frequencies to shift out the remaining (redundant) charge packets. Indeed, requiring clock signals &PHgr;
1
and &PHgr;
2
to operate between two frequencies leads to problems of control, increased circuit complexity and higher manufacturing costs.
To mitigate the above mentioned problems, the present invention utilizes a novel method and mechanism for use in CCD image-sensing devices which avoids image distortion without needing to shift the remaining (redundant) charge packets out of the CCD shift register. As a result, the processing and scanning speeds of CCD image-sensing devices and scanners can be accelerated. Attendant benefits include reduced circuit complexity and lower manufacturing costs.
SUM
Chen Michael
Wu Ivan
Avision Inc.
Birch & Stewart Kolasch & Birch, LLP
Vu Ngoc-Yen
LandOfFree
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