Method and structure for a low voltage CMOS integrated...

Details Method and structure for a low voltage CMOS integrated... Method and structure for a low voltage CMOS integrated...

2005-11-29

2005-11-29

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including high voltage or high power devices isolated from...

C257S501000, C257S506000, C257S371000, C257SE27067

Reexamination Certificate

active

06969901

ABSTRACT:
A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

REFERENCES:
patent: 5181095 (1993-01-01), Mosher et al.
patent: 5256582 (1993-10-01), Mosher et al.
patent: 5296393 (1994-03-01), Smayling et al.

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