Method and program for designing semiconductor integrated...

Details Method and program for designing semiconductor integrated... Method and program for designing semiconductor integrated...

2011-04-19

2011-04-19

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S051000

Reexamination Certificate

active

07930665

ABSTRACT:
The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from a memory unit variation coefficients of the property value of the cell corresponding to a dimension of a transistor constituting the cell; and performing a static timing analysis on the semiconductor integrated circuit by using the read variation coefficients and fundamental property value.

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Japanese Notice of Rejection Grounds, Partial English-language translation, mailed Jan. 18, 2011 for corresponding Japanese Patent Application No. 2006-296098.

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