Method and processor having bit-addressable scratch pad memory

Details Method and processor having bit-addressable scratch pad memory Method and processor having bit-addressable scratch pad memory

1977-11-07

1979-01-16

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

041352424

ABSTRACT:
A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address inputs of a dual port descriptor memory which stores descriptors. Two descriptors are simultaneously fetched from locations of the descriptor memory determined by the first and second address fields of the microinstruction. Each descriptor includes an address field which defines a location of the least significant bit of an operand in the scratch pad memory and a length field which defines the length of that operand. Two operands or partial operands are fetched from the scratch pad memory and transferred to a rotator circuit which automatically aligns the fetched operand to an arithmetic and logic unit which performs iterative and fractional operations. The disclosed system and method permit interpretation of virtual instructions without utilizing additional firmware subroutines to accomplish shifting or masking of variable length operands or to perform iterative operations or carry safe operations involving the operands to align them with fixed width hardware of the processor.

REFERENCES:
patent: 3739352 (1973-06-01), Packard
patent: 4032895 (1977-06-01), Lanza et al.

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