Electric heating – Heating devices – Combined with diverse-type art device
Reexamination Certificate
2001-06-26
2002-07-16
Jeffery, John A. (Department: 3742)
Electric heating
Heating devices
Combined with diverse-type art device
C219S243000, C219S085100, C219S085220, C228S180220, C228S193000, C324S765010
Reexamination Certificate
active
06420681
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention: This invention relates generally to semiconductor chip packages. More particularly, the present invention pertains to methods for electrical contact of an array of solder balls with a noncompliant surface.
State of the Art: The testing of packaged semiconductor devices has always presented problems to device manufacturers. Various types of tests may be conducted at different stages of manufacture. In the current state of the art, “wafer sort” electrical tests may be conducted prior to packaging to determine nonworking dies. Following packaging, various tests including environmental tests as well as parametric and functional electrical tests may be performed. A final test which is known as “burn-in” may optionally be conducted. The test includes temperature cycling over an extended period of time. Essential to the testing of individual dies is reliable electrical connection of all die leads to the test board, without incurring damage to the die or testing apparatus, and easy disassembly from the testing apparatus. While “permanent” wire connections are widely used, wirebonding is time consuming and expensive, and also makes the matching of device impedance to the substrate impedance very difficult to achieve. Much effort is being spent on developing alternative methods to reduce the time and expense of using wire bonds. The replacement of wire bonds with ball grid array (BGA) connections is becoming more common. Temporary conductive attachment of solder balls to e.g. a test board is less than satisfactory.
Temporary connection of device circuits to a test apparatus is known to present a variety of problems. The insert member into which a semiconductor die is placed for testing is typically noncompliant, i.e. ceramic or silicon, for example.
The current method for joining a ball grid array (BGA) to a noncompliant, i.e. rigid surface such as a silicon micromachined pocket interconnect or insert, is to apply, at ambient temperature, a relatively high compression force of about 22-30 grams-force per solder ball. Theoretically, all balls of the array should be pressed into mechanical and electrical contact with the insert pocket. The use of compressive forces lower than the above results in a further increased frequency of unsatisfactory electrical connections.
The presence of such unconnected solder balls in a BGA attachment formed under ambient conditions is believed to be due to a significant variability in ball diameter and “height” which the industry has been unable to eliminate. As a result, the applied force of about 22-30 grams-force or even more per ball is, in practice, insufficient to ensure the required contact of all balls of the array. Furthermore, the use of compression forces in excess of about 30 grams-force tends to damage the underlying material of the die, insert, and/or substrate. For example, effective connection of a 48 ball BGA array using solder balls of a nominal diameter may require in excess of about 1.5 kg-force. Such pressures exerted on a die for connection to a ceramic insert may damage the die and/or insert and/or substrate below the insert. The total force required for connection of larger arrays will be even more. In addition, the use of larger balls not only increases the absolute variation in ball diameter but the force required to sufficiently deform each ball for establishing the required temporary electrical connection. The problem also exists with smaller solder balls such as comprise a fine ball-grid-array (FBGA) of 0.0125 inches (0.325 mm) diameter balls, for example. With the smaller diameter solder balls, variation in ball placement location may have a greater effect than nonuniform ball diameters.
To date, the industry has continued to use relatively high compressive forces and necessarily accepted the increased occurrence of electrical connection failures of a BGA and/or damage to the die, insert or substrate.
Ball grid arrays are used in a variety of semiconductor devices. Illustrative of such prior art are U.S. Pat. No. 5,642,261 of Bond et al., U.S. Pat. No. 5,639,695 of Jones et al., U.S. Pat. No. 5,616,958 of Laine et al., U.S. Pat. No. 5,239,447 of Cotues et al., U.S. Pat. No. 5,373,189 of Massit et al., and U.S. Pat. No. 5,639,696 of Liang et al.
Semiconductor devices having dual sets of outer “leads”, e.g. twin BGA surfaces or a combination of e.g. J-leads and solder bumps, are shown in U.S. Pat. No. 5,648,679 of Chillara et al., U.S. Pat. No. 5,677,566 of King et al., and U.S. Pat. No. 5,668,405 of Yamashita.
Chip carriers of several configurations are described in U.S. Pat. No. 4,371,912 of Guzik, U.S. Pat. No. 4,638,348 of Brown et al., and Japanese publication 60-194548(1985).
Semiconductor devices joined in stacks are disclosed in U.S. Pat. No. 4,868,712 of Woodman, U.S. Pat. No. 4,841,355 of Parks, U.S. Pat. No. 5,313,096 of Eide, U.S. Pat. No. 5,311,401 of Gates, Jr. et al., U.S. Pat. No. 5,128,831 of Fox, III et al., U.S. Pat. No. 5,231,304 of Solomon, and U.S. Pat. No. 4,956,694 of Eide.
U.S. Pat. No. 5,637,536 of Val discloses a chip stacking configuration with solder ball connections.
U.S. Pat. No. 5,012,323 of Farnworth discloses a dual-die package having wire interconnections.
U.S. Pat. No. 4,761,681 of Reid discloses a multi-chip device having elevated (conductor covered mesa) interconnections.
Despite the advanced state of the art in lead interconnection, device packaging and testing, the temporary connection of semiconductor devices to testing apparatus and burn-in boards remains an area which needs improvement.
BRIEF SUMMARY OF THE INVENTION
The present invention pertains to methods for electrical contact of an array of solder balls with a noncompliant surface, that is, the mechanical and electrical contact of a ball grid array (BGA) to a relatively noncompliant contact set such as a silicon micromachined pocket interconnect (i.e. “insert”) for a test pad or burn-in board (BIB).
The present invention further provides a reliable BGA connection method and apparatus whereby the required pressure is much reduced to eliminate or significantly reduce compression-caused damage to the die, insert and/or substrate.
The present invention comprises methods and apparatus for softening solder bumps or balls so that all of the bumps/balls in an array readily conform to a matching array of conductive contact pockets or pads in another body. The array of solder bumps/balls is heated to a softening temperature lower than the melting point of the solder and quickly placed in slightly compressed engagement with the contact pockets or pads of a substrate. As compared to joining the arrays at ambient temperature, all bumps/balls of the BGA are reliably connected, and the connection is achieved at a much reduced pressure, avoiding damage to the die and/or substrate. In addition, much less stress is placed on the apparatus holding the packaged die, the insert and test board.
The softening temperature to which the solder is heated is below the melting temperature of the solder alloy.
A variety of heating apparatus and methods is disclosed, including direct heating of the bumps/balls, heating of the entire assembly, heating of a chuck holding the IC, heating of a chuck holding the insert, direct heating of the insert or substrate, etc. A temperature sensing circuit may also be incorporated into the insert, substrate, or substrate retaining socket for the purpose of measuring and controlling the temperature to which the bumps/balls are heated.
While electrical contact is readily maintained during electrical tests or burn-in by maintaining a small compressive force, ball contact is easily removed by discontinuing the compressive force and lifting the BGA from the insert or substrate to which it was electrically connected.
The invention is applicable to a wide variety of solder compositions, solder bump designs and ball diameters.
Other features of the invention will become clear from study of the following description and related figures.
REFERENCES:
patent: 4332341 (1982-06-01), Mine
Farnworth Warren M.
Hembree David R.
Jeffery John A.
Micro)n Technology, Inc.
TraskBritt
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