Method and pattern for reducing interconnect failures

Details Method and pattern for reducing interconnect failures Method and pattern for reducing interconnect failures

2003-05-30

2004-12-14

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S767000, C257S773000, C257S774000, C257S775000

Reexamination Certificate

active

06831365

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor structure and process. More particularly, the present invention relates to a method and pattern for reducing interconnect failures.
2. Description of Related Art
An integrated circuit is formed with many electronic elements and circuits shrunk on a microchip. High-density integrated circuits, such as very large scale integration (VLSI) circuits, are typically formed with two or more metal wires serving as multilevel structures to comply with a very high density of devices.
Interconnect structures, such as via plugs, connect the metal wires of the multilevel structure to form a complete circuit. The isolation structures in the metal wires are achieved by the formation of an inter-metal dielectric (IMD) layer. Recently, a process of fabricating the multilevel interconnect structure which forms the metal wire and the via plug at the same time has been developed, and is called a dual damascene process.
Aluminum (Al) is a commonly used conductive material for connecting various devices in the conventional semiconductor process because of its high conductivity, low price, and facility of deposition and etching. As the integrated density increases, the capacitance effect between the metal wires increases. Consequently, the resistance-capacitance time delay (RC delay time) increases, and cross talk between the metal wires becomes more frequent. The metal wire thus carries a current flow at a slower speed.
In the various factors, the inherent resistance of a metal wire and parasitic capacitance between two metal wires are crucial factors for determining the speed of the current flow. The parasitic capacitance can be reduced by insulating metal wiring layers with low k (dielectric constant) materials, the dielectric constants thereof being generally lower than 3.5. To achieve the reduction of the resistances of metal wires, materials with low resistances are selected for fabricating the metal wires. Copper (Cu) having a relatively high melting point, low resistance (about 1.7 &mgr;&OHgr;-cm) and high anti electro-migration ability gradually has become the new material of choice for replacing aluminum.
FIG. 1A
illustrates a schematic view of a conventional via plug structure between two metal layers. The via plug structure
100
is a metal layer/dielectric layer/metal layer structure. A metal layer
104
having a line extension attached thereto is connected to a metal layer
108
by a via plug
108
.
FIG. 1B
illustrates a partial side view of FIG.
1
A. The other portions of the two metal layers
104
and
106
are insulated by a dielectric layer
102
as illustrated in FIG.
1
B.
However, it is hard to avoid formation of some vacancies on the edges of grains of the metal layer
104
as the metal layer
104
is formed. As a result of a stress gradient, the vacancies are driven to pass through the line extension
104
a
, and collect at the bottom of the via plug
108
, named via plug bottom
112
, so as to form stress-induced voids (SIVs). The SIV is at the via plug bottom
112
and causes the via plug
108
to be interrupted, thereby generating interconnect failures.
The SIV formation mechanism is usually explained as vacancies in the metal layer being driven by the thermal stress gradient to a certain area to form voids. The thermnal stress gradient results from the stress variations of different areas with different thermal expansion constants. For an integrated circuit, the variations of temperature during processing or operating, and the mismatching of different materials, generally generate a thermal stress gradient.
For example, when there are wires with different widths in the metal layers, such as the metal layers
104
and the line extension
104
a
in
FIG. 1A
, a thermal stress gradient is generated due to their different area dimensions as their temperatures are varying. The voids resulting from the thermal stress gradient especially tend to form at the via plug bottom
112
, because the via plug bottom
112
is the lowest stress area. Thus the via plug
108
is interrupted.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide method and pattern for reducing interconnect failures, which satisfies the need to avoid the via plug bottom being interrupted by voids.
In accordance with the foregoing and other objectives of the present invention, a method and a pattern for reducing the interconnect failures are described. At least one assistant pattern, such as a 2-D dummy line extension or a 3-D dummy via plug, is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from being generated at the bottom of a via plug which connects the two metal layers.
When a via plug connects one metal layer and a line extension attached to the other metal layer, the invention improves the interconnect structure by imposing at least one turning corner upon the line extension, the turning corner being located between the other metal layer and the via plug. The turning corner is the high stress area and prevents the vacancies of the other metal layer from being driven to the line extension, therefore keeping the via plug bottom from being interrupted.
In one preferred embodiments of the present inventions, a material of the two metal layers, the via plug and the assistant pattern is copper, and a material of the dielectric layer is a low k material.
A higher quantity of assistant pattern has a greater ability of dissipating vacancies to prevent the voids from being generated at the via plug bottom. Additionally, if the assistant pattern is nearer the line extension, the probability of sharing the vacancies is higher and the effect of preventing the voids from being generated at the via plug bottom is therefore also better.
Besides, the dummy via plug is not located at the line extension or the junction of the line extension and the metal layer. If it were, the vacancies gathered by the dummy via plug would form voids, and then the line extension or the junction would be interrupted, resulting in the metal layer being interrupted.
In another preferred embodiment of the invention, a turning corner is imposed upon the line extension attached to the metal layer. The turning corner is located between the metal layer and the via plug. The angle of the turning corner is 90 degrees, but other turning corners with other degrees that are high stress areas are also applicable in the present invention.
In addition, more than one turning corner can be used. Multiple turning corners imposed upon the line extension improve void prevention at the via plug bottom.
In conclusion, the dummy line extensions and the dummy vias not only reduce the area dimension having a local stress gradient, called an effective vacancy diffusion area, that drives the vacancies towards the via plug bottom, but also share the vacancies and diversify the destinations of the traveling vacancies.
The turning corner provides a high stress area in the line extension connecting with the via plug, which increases the stress migration incubation and reduces the probability of interconnect failures caused by the stress-induced voids. The stress migration-related interconnect reliability is thus improved.
It is to be understood that both the foregoing general description and the following detailed description are examples, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5506450 (1996-04-01), Lee et al.
patent: 6329719 (2001-12-01), Nakamura
patent: 6417572 (2002-07-01), Chidambarrao et al.
patent: 6650010 (2003-11-01), Davis et al.

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