Method and pattern for avoiding micro-loading effect in an etchi

Details Method and pattern for avoiding micro-loading effect in an etchi Method and pattern for avoiding micro-loading effect in an etchi

1999-02-11

2000-11-21

Utech, Benjamin L.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

257210, 257211, 257224, 438 18, 438719, 438720, 438725, H01L 2710

Patent

active

061506788

ABSTRACT:
A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.

REFERENCES:
patent: 4916514 (1990-04-01), Nowak
patent: 5032890 (1991-07-01), Ushiku et al.
patent: 5278105 (1994-01-01), Eden et al.
patent: 5598010 (1997-01-01), Uematsu
patent: 5684316 (1997-11-01), Lee

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