Method and packaging structure for optimizing warpage of...

Details Method and packaging structure for optimizing warpage of... Method and packaging structure for optimizing warpage of...

2006-04-11

2006-04-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S737000, C257S778000, C438S108000, C438S106000, C438S457000

Reexamination Certificate

active

07026706

ABSTRACT:
An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

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patent: 2002/0027294 (2002-03-01), Nenhaus et al.
patent: 0 294 015 (1988-12-01), None
patent: 11-186326 (1999-07-01), None

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