Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1999-11-18
2004-08-10
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C324S658000, C324S677000
Reexamination Certificate
active
06775627
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or software for accurate capacitance acquisition generally and, more particularly, to a method and/or software for determining the capacitance of an analog/mixed signal circuit.
BACKGROUND OF THE INVENTION
There are several conventional methods for CMOS cell input pin capacitance acquisition. Bipolar junction transistor BJT-CML technology requires additional special characteristics in order to determine the capacitance. The characteristics for determining the capacitance in BJT-CML technology is not clear. The conventional methods for CMOS cell capacitance acquisition is not suitable for BJT-CML cell capacitance acquisition. Currently, conventional approaches are not available for BJT-CML cell input pin capacitance acquisition.
Referring to
FIG.1
, a conventional circuit
10
that is used for pin capacitance acquisition is shown. The voltages across the pin capacitance are defined by the following equation EQ1:
v=V
(1
−e
−t/RC
) EQ1
By definition, the RC time constant &tgr; is the product of R and C and is defined by the following equation EQ2:
&tgr;=
RC
EQ2
At time t=&tgr; the voltage v is defined by the following equation EQ3:
v=V
(1
−e
−t/RC
)=0.63
V
EQ3
Using a known value of R and measuring the value of t at which the charging voltage v is 0.63 V, the pin capacitance is found by the following equation EQ4:
C=t/R
EQ4
Referring to
FIG. 2
, a graph illustrating voltage versus time of the circuit
10
. The circuit
10
is sensitive to the value of R. The acquired capacitance by this method for the same pin could have 100% to 1000% variation with different values R.
Another conventional method for CMOS cell capacitance acquisition, a so-called an imaginary current method, may be defined by the following equations:
V/l
m
=1/(
WC
)
W
=2
&pgr;f
C=l
m
/(2
&pgr;fV
) (when
V
=1
v
)
=
l
m
/(2
&pgr;f
)
Using a known value of stimulus frequency f, and measuring the value of imaginary current l
m
, the pin capacitance can be acquired. However, the imaginary current method is very sensitive to the choice of the stimulus frequency f. The acquired capacitance by this method for the same pin could have up to 1000% variation based on different values of the stimulus frequency f.
Another conventional approach for CMOS cell capacitance acquisition, a so-called impedance method, may be defined by the following equations:
Z
=(
R
2
+(
WC
)
−2
)
½
Z
2
=R
2
+(
WC
)
−2
(
W
=2
&pgr;f
)
C
2
=(1/(2
&pgr;f·Z
))
2
·((
WCR
)
2
+1)
tan &phgr;=(1/(
WCR
))
C
=(1/(2
&pgr;f·Z
))·((tan &phgr;)
−2
+1)
½
When R is small, WCR<<1,
C
=(1/(2
&pgr;f·Z
))
Z=V
rms
/l
rms
Using a known value for the stimulus frequency f, and measuring the value of V
rms
and l
rms
, the pin capacitance can be acquired. The impedance method is also very sensitive to the choice of the stimulus frequency f. The acquired capacitance calculated by the impedance method for the same pin could have up to 1000% variation based on different values of f.
Another conventional method for CMOS cell capacitance acquisition is a so-called I/(DV/DT) method. By definition, capacitance C is defined by the following equation:
C=dQ/dV
On the other hand,
dQ=I·dt
dQ=C·dV=I·dt
C=I
/(
dV/dt
)
where V is input stimulus voltage. If a linear source voltage is used, dV/dt is a constant.
K=dV/dt
C=I/K
Take average in the range T,
(∫
o
T
Cdt
)/
T
=((∫
o
T
Idt
)/
T
)·(1
/K
)
Avg(
C
)=Avg(
I
)/
K
Measure Avg(I)→Avg(C)→C
FIG. 3
is a graph illustrating voltage as an input and current as an output, each versus time for the I/(DV/DT) method. The I/(DV/DT) method is still sensitive to input slope rate K for analog signals (BJT-CML), but may provide better tolerance (e.g., −50% to 50%) than other conventional methods.
None of the conventional methods described is targeted to bi-cmos technology. Additionally, the conventional methods described are not normally accurate enough for input pin capacitance acquisition.
SUMMARY OF THE INVENTION
The present invention concerns a method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance.
The objects, features and advantages of the present invention include providing a method and/or software that may allow for (i) capacitance acquisition of BJT-CML cells, and/or (ii) characterization of a BJT-CML cell library.
REFERENCES:
patent: 4617512 (1986-10-01), Horner
patent: 5744964 (1998-04-01), Sudo et al.
patent: 5844412 (1998-12-01), Norton
patent: 4334630 (1995-04-01), None
Boes, II Barry A.
Liu Zhiwu
Maheshwari Dinesh
Cypress Semiconductor Corp.
Hoff Marc S.
Kim Paul
Maiorana P.C. Christopher P.
LandOfFree
Method and/or software for determining the capacitance of an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and/or software for determining the capacitance of an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and/or software for determining the capacitance of an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3360632