Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1998-09-30
2003-02-25
Rinehart, Mark H. (Department: 2152)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C370S359000, C370S419000, C370S463000
Reexamination Certificate
active
06526451
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of buffer structures, and more particularly, to a method and network device for creating buffer structures in a shared external memory that exists between a host and network device.
BACKGROUND OF THE INVENTION
Data networks have become increasingly important in day-to-day activities and business applications. Most of these networks are a packet-switched network, such as the Internet, which uses a Transmission Control Protocol (TCP) and an Internet Protocol (IP), frequently referred to as TCP/IP. The Transmission Control Protocol manages the reliable reception and transmission of network traffic, while the Internet Protocol is responsible for routing to ensure that packets are sent to a correct destination.
In a typical network, a mesh of transmission links are provided, as well as switching nodes and end nodes. End nodes typically ensure that any packet is received and transmitted on the correct outgoing link to reach its destination. The switching nodes are typically referred to as packet switches, or routers, or intermediate systems. The sources and destinations in data traffic (the end nodes) can be referred to as hosts and end systems. These hosts and end systems typically are the personal computers, work stations and other terminals.
To help move information between computers, the open system interconnection (OSI) model has been developed. Each problem of moving information between computers is represented by a layer in the model, and thus, establishes a framework for standards. Two systems communicate only between layers in a protocol stack. However, it is desirable to communicate with a pure layer in the other system, and to achieve such results, information is exchanged by means of protocol data units (PDUs), also known as packets. The PDUs include headers that contain control information, such as addresses, as well as data. At a source, each layer adds its own header, as is well known to those skilled in the art. The seven layers, starting at the physical layer, include: (1) physical; (2) data link; (3) network; (4) transport; (5) session; (6) presentation; and (7) application layers.
The network systems typically use routers that can determine optimum paths, by using routing algorithms. The routers also switch packets arriving at an input port to an output port based on the routing path for each packet. The routing algorithms (or routing protocols) are used to initialize and maintain routing tables that consist of entries that point to a next router to send a packet with a given destination address. Typically, fixed costs are assigned to each link in the network and the cost reflects link bandwidth and/or costs. The least cost paths can be determined by a router after it exchanges network topology and link cost information with other routers.
The two lower layers, the physical and data link layers, are typically governed by a standard for local area networks developed by the IEEE 802 Committee. The data link layer is typically divided into two sublayers, the logical link control (LLC) sublayer, which defines functions such as framing, flow control, error control and addressing. The LLC protocol is a modification of the HDLC protocol. A medium access control (MAC) sublayer controls transmission access to a common medium.
High-level data link control (HDLC) is a communications control procedure for checking the accuracy of data transfer operations between remote devices, in which data is transferred in units known as frames, and in which procedures exist for checking the sequence of frames, and for detecting errors due to bits being lost or inverted during transfer operations. There are also functions which control the set-up and termination of the data link. In HDLC, the bit synchronous data communication across a transmission link is controlled. HDLC is included in the ITU packet-switching interface standard known as X.25.
Programmable HDLC protocol controllers are commonly used in these systems. An HDLC controller is a computer peripheral-interface device which supports the International Standards Organization (ISO) high-level-data-link-control (HDLC). It reduces the central processing unit or microprocessor unit (MPU) software by supporting a frame-level instruction set and by hardware implementation of the low-level tasks associated with frame assembly-disassembly and data integrity.
Most communication protocols are bit-oriented, code-dependent, and ideal for full duplex communication. Some common applications include terminal-to-terminal, terminal-to-MPU, MPU-to-MPU, satellite communication, packet switching, and other high-speed data links.
A communication controller relieves a central MPU of many of the tasks associated with constructing and receiving frames. A frame (sometimes referred to as a packet) is a single communication element which can be used for both link-control and data-transfer purposes.
Most controllers include a direct memory access (DMA) device or function which provides access to an external shared memory resource. The controller allows either DMA or non-DMA data transfers. The controller accepts a command from the MPU, executes the command, and provides an interrupt and result back to the MPU.
Networking devices, including routers, typically have a number of descriptor rings, consisting of individual descriptors and associated buffers. The descriptor rings act as arrays of indirect addressing pointers, e.g., the descriptors, which inform where the buffer memory is located in an external memory that is part of a host system and shared with the network device. Typically, each individual descriptor has an ownership bit, which together with other parts of the descriptor, allows a handshaking between a network device and host system.
It has also been advantageous to have at least one descriptor ring for each activated channel (or port) within a network device. Each channel includes a transmit and receive FIFO memory, and preferably there would be a descriptor ring for each FIFO memory. If there were four ports, then there would be eight descriptor rings, one for the transmit FIFO memory and one for the receive FIFO memory. Usually, the host software implements these data and buffer structures in memory. The host, therefore, includes complicated software to build the various descriptor rings and buffers.
However, with the advent of multi-channel devices, the configuration and set up required to build these structures by the host system has become increasingly complicated and time consuming. This is especially relevant because of the geometry and length of descriptor rings and the sizes of their associated buffers. Additionally, various networking devices may require different types of descriptor rings and different size frame data buffers depending on their application and the type of industry. A descriptor ring can vary in size, including and usually ranges between 10-500 descriptors, while the frame data buffers often vary from 256 bytes up to 2K or 64K bytes. Buffer size is generally selected based upon the maximum supported frame size of interfacing networks. Overall memory allocated per port is often in the two megabyte range.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method and network device that can build data structures using descriptor rings within a network device to free up resources within a host system.
The present invention is advantageous because the network device itself assumes the responsibility for the creation of buffer structures, such as frame data buffers and the associated descriptor rings and descriptors. The network device constructs the transmit and/or receive descriptor rings in an externally shared memory with the host system. The parameters dictating the number of descriptors in need of the receive or transmit descriptor rings and their respective frame data buffer dimensions are communicated via a parameter block (an administration block) that is exchanged between the host system and the network device at initi
Jorgenson Lisa K.
Prieto Beatriz
Regan Christopher F.
Rinehart Mark H.
STMicroelectronics Inc.
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