Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1997-04-15
2000-12-12
Flynn, Nathan
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
348512, 348515, 348516, 348518, G06F 300, G06F 1300, H04N 9475
Patent
active
061605484
ABSTRACT:
A method and system for synchronizing modules associated with audiovisual devices, generally for use with a digital non-linear editor. A logical clock communicates information, including time and state (clock operating mode) information, to hardware and software modules through a synchronization port. The synchronization ports convert the time information into values recognizable by the module, and offset the time as needed to maintain synchronization. The state information may effect module commands for controlling audiovisual devices, such as rewind, playback and capture commands to tape players, timed such that various devices having different preparatory timing requirements are synchronized. State information, such as information indicating that a device is ready, may be returned by the modules. Video editing features such as scrubbing, looping and frame-stepping are supported by the mode information that is communicated between the clock and the synchronization ports.
REFERENCES:
patent: 5751368 (1998-05-01), Cooper
patent: 5861880 (1999-01-01), Shimizu et al.
patent: 5872565 (1999-02-01), Greaves et al.
patent: 5917482 (1999-06-01), Putnam
Barr Adam D.
Hill Raymond
Lea Christopher B.
Flynn Nathan
Vu Ngoc K.
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