Method and mechanism for performing clearance-based zoning

Details Method and mechanism for performing clearance-based zoning Method and mechanism for performing clearance-based zoning

2011-03-08

2011-03-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S052000, C716S111000

Reexamination Certificate

active

07904862

ABSTRACT:
A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.

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