Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2005-01-18
2005-01-18
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S183000, C702S189000, C702S190000
Reexamination Certificate
active
06845341
ABSTRACT:
A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.
REFERENCES:
patent: 5668732 (1997-09-01), Khouja et al.
patent: 5953519 (1999-09-01), Fura
patent: 6075932 (2000-06-01), Khouja et al.
patent: 6163763 (2000-12-01), Cox et al.
patent: 6182258 (2001-01-01), Hollander
patent: 6347388 (2002-02-01), Hollander
patent: 6470482 (2002-10-01), Rostoker et al.
patent: 6530054 (2003-03-01), Hollander
patent: 6581191 (2003-06-01), Schubert et al.
patent: 6618839 (2003-09-01), Beardslee et al.
Ferrari, Alberto et al., “Design and Implementation of Dual Processor Platform for Power-train Systems”, Proceedings of the 2000 International Congress on Transportation Electronics, Oct. 2000, pp. 325-331, Society of Automotive Engineers, Inc., Warrendale, PA.
Baliani, M. et al., “HW/SW Codesign of an Engine Management System”, Proceeding of Design, Automation and Test in Europe Conference, Mar. 2000, Munich, DE.
Ferrari, Alberto et al., “System Design: Traditional Concepts and New Paradigms”, Proceedings of the 1999 Int. Conf. on Comp. Des., Oct. 1999, Austin.
Chang, Henry et al., “Surviving the SOC Revolution, A Guide to Platform-Based Design”, 1999, Kluwer Academic Publishers, Norwell, MA.
Clouard, Alain et al., “Towards Bridging the Precision Gap Between SOC Transactional and Cycle-Accurate Levels”, Design, Automation and Test in Europe Conference, Munich, Mar. 2002.
Carbognani, Franco et al., “Qualifying Precision of Abstract SystemC Models Using the SystemC Varification Standard”, ACM/SIGDA Date '03, Munich, Germany, Mar. 3-7, 2003.
Schirrmeister, Frank et al., “Virtual Component Co-Design—Facilitating a Wn-Win Relationship between IP Integrators and IP Providers”, IP Conference, Edinburgh, Nov. 1999.
Siegmund, Robert et al., “SystemCsv: An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design”, IEEE, 2001.
De La Torre, E. et al., “Model Generation of Test Logic for Macrocell Based Designs”, IEEE, 1996.
PCT International Search Report, International Application No. PCT/US03/15344, Aug. 8, 2003.
Beverly Aaron
Carbognani Franco
Gupta Shampa
Parikh Prakash
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Hoff Marc S.
Suarez Felix
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