Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-05-03
2011-05-03
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S130000, C716S137000
Reexamination Certificate
active
07937681
ABSTRACT:
A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.
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Gillmor Wiley
Katz Walter
Lawson Randall
Wadland Ken
Woodward, Jr. Richard Allen
Cadence Design Systems Inc.
Lin Sun J
Memula Suresh
Vista IP Law Group LLP
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