Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-03-15
2011-03-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S124000
Reexamination Certificate
active
07908579
ABSTRACT:
Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern.
REFERENCES:
patent: 5771045 (1998-06-01), Ghavam et al.
patent: 7246343 (2007-07-01), Joshi et al.
patent: 2006/0048091 (2006-03-01), Joshi et al.
patent: 2006/0236299 (2006-10-01), Sahouria et al.
patent: 3176784 (1991-07-01), None
patent: 2005058029 (2005-06-01), None
Sato, M. et al. “A Theoretically Optimal and Practically Fast Algorithm for VLSI Geometric Design Rule Verification” IEEE International Symposium on Circuits and Systems (ISCAS '88), Jun. 7-9, 1988, vol. 2, pp. 1445-1448.
English translation of abstract for JP 3176784 published on Jul. 31, 1991.
Belousov Alexander
Cadouri Eitan
Gratchev Andrei
Irmatov Anwar
Ryjov Alexander
Cadence Design Systems Inc.
Siek Vuthe
Vista IP Law Group LLP
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