Method and means for testing integrated circuits

Details Method and means for testing integrated circuits Method and means for testing integrated circuits

1983-01-27

1985-10-08

Atkinson, Charles E.

Excavating

324 73R, 371 25, 371 27, G01R 3128, G06F 1100

Patent

active

045464723

ABSTRACT:
Data processing logic (10) is fabricated on an integrated circuit device and is outputted to a plurality of output pins (1-N). A number of these pins (34, 36, 38) which are normally function outputs, and a reset pin (24), are used to invoke a test state on the integrated circuit device. Test control logic generates two test flags (TA, TB) in response to test signals on two of these pins (34, 36). These two test flags are decoded (14, 18, 20, 22) to control all signal output pins (1-N) from the integrated circuit device by forcing a high-level, low-level, or high-impedance condition, as selected by external stimulus at the output pins, regardless of the condition of the internal circuitry on the integrated circuit device. A test flag TC (60) is generated in response to a test signal on pin (38). This TC flag is used to signal the data processing logic (10) to initiate a functional self-check operation.

REFERENCES:
patent: 3657527 (1972-04-01), Kassabgi et al.
patent: 3714571 (1973-01-01), Walker
patent: 3976940 (1976-08-01), Chau et al.
patent: 4092589 (1978-05-01), Chau et al.
patent: 4176258 (1979-11-01), Jackson
A. Mastrocola, Effective Utilization of In-Circuit Techniques When Testing Complex Digital Assemblies, Automatic Testing & Test and Measurement 1981, Conference, Weisbaden, W. Germany, Mar. 1981, pp. 106-117.

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